IP Library › Granted Patent US 12,748,908
Granted Patent B2
US 12,748,908 · App. 18/226,188 · Granted Sep 29, 2026

Statistical graph circuit component probability model for an integrated circuit design

Inventors: Xiang Gao (San Jose, CA); Hursh Naik (Sunnyvale, CA); Bryan Charles Walsh (Coon Rapids, MN); Manish Sharma (San Jose, CA)
Assignee: Synopsys, Inc.
G06F30/398G06F30/31G06F30/27G06F30/3308G06F30/367G06N3/047G06N3/08G06N5/00G06N7/01G06N20/00
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Quick Facts
Patent No.
US 12,748,908
App. No.
18/226,188
Granted
Sep 29, 2026
Kind
B2
Abstract

A system and method predicts performance of a circuit design by receiving circuit design training data and circuit design test data. The circuit design training data includes training nodes and training paths. The training paths connect the training nodes including circuit components. The circuit design test data includes a first test node and a second test node. Further, testing information is determined for the circuit components of each training path from the circuit design training data. A statistical representation of the circuit design test data is determined based on the testing information and the circuit design test data, and first test information for a test path connecting the first test node with the second test node is determined based on the statistical representation.

Claims (33)

1 . A method comprising:

receiving circuit design training data and circuit design test data, the circuit design training data including training nodes and training paths, wherein the training paths connect the training nodes including circuit components, and wherein the circuit design test data includes a first test node and a second test node;

determining testing information for the circuit components of each training path from the circuit design training data;

determining, by a processing device, a statistical representation of the circuit design test data based on the testing information and the circuit design test data; and

determining first test information for a test path connecting the first test node with the second test node based on the statistical representation.

2 . The method of claim 1 , wherein the testing information includes one or more of statistical information and circuit parameter information.

3 . The method of claim 1 , wherein determining the testing information comprises determining a hashing table associating each circuit component type with respective testing information.

4 . The method of claim 3 , wherein the statistical representation is determined from the hashing table and includes at least one or more of a statistical graph model and a statistical path model.

5 . The method of claim 1 , wherein determining the testing information comprises determining a bookkeeping graph based on the training nodes and the training paths.

6 . The method of claim 5 , wherein the bookkeeping graph comprises edges and nodes, and the testing information is associated with the edges.

7 . The method of claim 5 , wherein the bookkeeping graph comprises edges and nodes, and the testing information is associated with the nodes.

8 . The method of claim 5 , wherein the first test information is determined from the bookkeeping graph and includes a statistical graph model.

9 . The method of claim 5 , wherein determining the first test information for the test path comprises combining the statistical representation determined from two or more bookkeeping graphs.

10 . The method of claim 1 , wherein determining the testing information for the circuit components of each training node from the circuit design training data comprises determining neighborhood information for each of the circuit components.

11 . A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

receive circuit design training data and circuit design test data, the circuit design training data including training nodes and training paths, wherein the training paths include connect the training nodes including circuit components, and wherein the circuit design test data includes a first test node and a second test node;

determine testing information for the circuit components of each training path from the circuit design training data;

determine a statistical representation of the circuit design test data based on the testing information and the circuit design test data; and

determine first test information for a test path connecting the first test node with the second test node based on the statistical representation.

12 . The non-transitory computer readable medium of claim 11 , wherein the testing information includes statistical information or circuit parameter information.

13 . The non-transitory computer readable medium of claim 11 , wherein determining the testing information comprises determining a hashing table associating each circuit component type with respective testing information.

14 . The non-transitory computer readable medium of claim 13 , wherein the statistical representation is determined from the hashing table and includes at least one of a statistical graph model and a statistical path model.

15 . The non-transitory computer readable medium of claim 11 , wherein determining the testing information comprises determining a bookkeeping graph based on the training nodes and the training paths.

16 . The non-transitory computer readable medium of claim 15 , wherein the statistical representation is determined from the bookkeeping graph and includes a statistical graph model.

17 . The non-transitory computer readable medium of claim 11 , wherein determining the testing information for the circuit components of each training node from the circuit design training data comprises determining neighborhood information for each of the circuit components.

18 . A system comprising:

a memory storing instructions; and

a processing device, coupled with the memory and configured to execute the instructions, the instructions when executed cause the processing device to:

receive design training data and design test data, the design training data including training nodes and training paths, wherein the training paths include components and connect the training nodes, and wherein the design test data includes a first test node and a second test node;

determine testing information for the components of each training path from the design training data, the testing information includes entries including values associated with the components; and

determine test information for a test path connecting the first test node with the second test node based on the entries of the components associated with the test path.

19 . The system of claim 18 , wherein determining the testing information comprises determining a bookkeeping graph, and wherein the entries are associated with nodes of the bookkeeping graph or edges of the bookkeeping graph.

20 . The system of claim 18 , wherein determining the testing information comprises determining a hashing table, and wherein the entries are associated with keys of the hashing table.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2023
From: GAO, XIANG; NAIK, HURSH; WALSH, BRYAN CHARLES; SHARMA, MANISH
To: SYNOPSYS INCORPORATED
Reel/Frame 064595/0120 →
Continuity (2)
Provisional Application 63392436 · Jul 26, 2022
Related Publication 20240037313A1 · Feb 1, 2024
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