Gate driver and display device including the same
The present disclosure relates to gate driver and display device including the same. According to an aspect of the present disclosure, a gate driver includes: a plurality of stages which is dependently connected to each other, each of the plurality of stages includes: a node controller configured to control voltages of a Q node, a Q 1 node, a Q 2 node, a QB node, a QB 1 node, and a QB 2 node based on a first clock signal and a second clock signal; a carry signal output unit configured to output a carry signal to a next stage based on the voltages of the Q 1 node and the QB 1 node; and a scan signal output unit configured to output a scan signal to a scan line based on the voltages of the Q node and the QB node, and a width of the scan signal may be determined by a toggling timing of the first clock signal and a toggling timing of the second clock signal.
1 . A gate driver, comprising:
a plurality of stages which are connected to one another,
wherein each of the plurality of stages includes:
a node controller configured to control voltages of a Q node, a Q 1 node, a Q 2 node, a QB node, a QB 1 node, and a QB 2 node based on a first clock signal and a second clock signal;
a carry signal output unit configured to output a carry signal to a next stage based on the voltages of the Q 1 node and the QB 1 node; and
a scan signal output unit configured to output a scan signal to a scan line based on the voltages of the Q node and the QB node,
wherein a width of the scan signal is determined by a toggling timing of the first clock signal and a toggling timing of the second clock signal,
wherein the carry signal output unit includes:
an eighth transistor including a first electrode connected to a gate low voltage supply line, a gate electrode connected to the Q 1 node, and a second electrode connected to a carry signal output terminal; and
a ninth transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the QB 1 node, and a second electrode connected to the carry signal output terminal; and
wherein the carry signal output unit further includes:
a fourth capacitor which is connected between the gate electrode and the second electrode of the eighth transistor; and
a fifth capacitor which is connected between the gate low voltage supply line and the carry signal output terminal.
2 . The gate driver according to claim 1 ,
wherein the scan signal output unit includes:
a first transistor including a first electrode connected to a gate low voltage supply line, a gate electrode connected to the Q node, and a second electrode connected to a scan signal output terminal;
a second transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the QB node, and a second electrode connected to the scan signal output terminal; and
a first capacitor connected between the gate electrode and the second electrode of the first transistor.
3 . The gate driver according to claim 2 ,
wherein when the second clock signal is toggled from a high level to a low level, the first capacitor is configured to bootstrap the Q node.
4 . The gate driver according to claim 1 ,
wherein when the first clock signal is toggled from a high level to a low level, the fourth capacitor is configured to bootstrap the Q 1 node.
5 . The gate driver according to claim 1 ,
wherein the node controller includes:
a first node controller configured to control the Q 2 node and the QB 2 node;
a second node controller configured to control the Q 1 node and the QB 1 node; and
a third node controller configured to control the Q node and the QB node.
6 . The gate driver according to claim 5 ,
wherein the first node controller includes:
a third transistor including a first electrode connected to a start signal input terminal or a carry signal output terminal of a previous stage, a gate electrode connected to a first clock signal supply line, and a second electrode connected to the Q 2 node;
a seventh transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the start signal input terminal or the carry signal output terminal of the previous stage, and a second electrode connected to the QB 2 node; and
a third capacitor which is connected between the first clock signal supply line and the QB 2 node.
7 . The gate driver according to claim 5 ,
wherein the second node controller includes:
a fourth transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the Q 2 node, and a second electrode connected to the QB 1 node;
a fifth transistor including a first electrode connected to a first clock signal supply line, a gate electrode connected to the QB 2 node, and a second electrode connected to the QB 1 node;
a sixth transistor including a first electrode connected to the Q 2 node, a gate electrode connected to a gate low voltage supply line, and a second electrode connected to the Q 1 node; and
a second capacitor which is connected between the gate high voltage supply line and the QB 1 node.
8 . The gate driver according to claim 5 ,
wherein the third node controller includes:
a tenth transistor including a first electrode connected to the Q 1 node, a gate electrode connected to a first clock signal supply line, and a second electrode connected to the Q node;
an eleventh transistor including a first electrode connected to the QB 1 node, a gate electrode connected to the first clock signal supply line, and a second electrode connected to the QB node;
a twelfth transistor including a first electrode connected to the gate low voltage supply line, a gate electrode connected to a second clock signal supply line, and a second electrode connected to the Q node; and
a thirteenth transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the second clock signal supply line, and a second electrode connected to the QB node.
9 . The gate driver according to claim 1 ,
wherein when the first clock signal is toggled from a high level to a low level, the scan signal is toggled from a low level to a high level, and when the second clock signal is toggled from a high level to a low level, the scan signal is toggled from a high level to a low level.
10 . The gate driver according to claim 1 ,
wherein when the first clock signal is toggled from a high level to a low level, the carry signal is toggled.
11 . The gate driver according to claim 1 , wherein a plurality of transistors included in each of the plurality of stages is p-type transistors.
12 . A display device, comprising:
a display panel including an active area in which a plurality of pixels is disposed; and
a gate driver including a plurality of stages which are connected to one another,
wherein each of the plurality of stages includes:
a node controller configured to control voltages of a Q node, a Q 1 node, a Q 2 node, a QB node, a QB 1 node, and a QB 2 node based on a first clock signal and a second clock signal;
a carry signal output unit configured to output a carry signal to a next stage based on the voltages of the Q 1 node and the QB 1 node; and
a scan signal output unit configured to output a scan signal to a scan line based on the voltages of the Q node and the QB node,
wherein a width of the scan signal is determined by a toggling timing of the first clock signal and a toggling timing of the second clock signal,
wherein the carry signal output unit includes:
an eighth transistor including a first electrode connected to a gate low voltage supply line, a gate electrode connected to the Q 1 node, and a second electrode connected to a carry signal output terminal; and
a ninth transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the QB 1 node, and a second electrode connected to the carry signal output terminal, and
wherein the carry signal output unit further includes:
a fourth capacitor connected between the gate electrode and the second electrode of the eighth transistor; and
a fifth capacitor which is connected between the gate low voltage supply line and the carry signal output terminal.
13 . The display device according to claim 12 ,
wherein the scan signal output unit includes:
a first transistor including a first electrode connected to a gate low voltage supply line, a gate electrode connected to the Q node, and a second electrode connected to a scan signal output terminal;
a second transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the QB node, and a second electrode connected to the scan signal output terminal; and
a first capacitor which is connected between the gate electrode and the second electrode of the first transistor.
14 . The display device according to claim 12 ,
wherein the node controller includes:
a first node controller configured to control the Q 2 node and the QB 2 node;
a second node controller configured to control the Q 1 node and the QB 1 node; and
a third node controller configured to control the Q node and the QB node.
15 . The display device according to claim 14 , wherein the first node controller includes:
a third transistor including a first electrode connected to a start signal input terminal or a carry signal output terminal of a previous stage, a gate electrode connected to a first clock signal supply line, and a second electrode connected to the Q 2 node;
a seventh transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the start signal input terminal or the carry signal output terminal of the previous stage, and a second electrode connected to the QB 2 node; and
a third capacitor which is connected between the first clock signal supply line and the QB 2 node.
16 . The display device according to claim 14 ,
wherein the second node controller includes:
a fourth transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the Q 2 node, and a second electrode connected to the QB 1 node;
a fifth transistor including a first electrode connected to a first clock signal supply line, a gate electrode connected to the QB 2 node, and a second electrode connected to the QB 1 node;
a sixth transistor including a first electrode connected to the Q 2 node, a gate electrode connected to a gate low voltage supply line, and a second electrode connected to the Q 1 node; and
a second capacitor which is connected between the gate high voltage supply line and the QB 1 node.
17 . The display device according to claim 14 ,
wherein the third node controller includes:
a tenth transistor including a first electrode connected to the Q 1 node, a gate electrode connected to a first clock signal supply line, and a second electrode connected to the Q node;
an eleventh transistor including a first electrode connected to the QB 1 node, a gate electrode connected to the first clock signal supply line, and a second electrode connected to the QB node;
a twelfth transistor including a first electrode connected to a gate low voltage supply line, a gate electrode connected to a second clock signal supply line, and a second electrode connected to the Q node; and
a thirteenth transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the second clock signal supply line, and a second electrode connected to the QB node.
18 . The display device according to claim 14 ,
wherein each of the plurality of pixels includes both a p-type transistor and an n-type transistor.