3D memory block having low-resistance source/drain buried layer stacked architecture
View Patent ↗The present disclosure provides a memory block, a memory cell, and a manufacturing method of a memory block. The memory block includes a memory array, including: a plurality of columns of semiconductor stacked strip structures that are spaced apart along a row direction; wherein each column of stacked strip structure extends along a column direction and comprises at least one drain region semiconductor strip, at least one channel semiconductor strip, and at least one source region semiconductor strip that are stacked along a height direction. Each drain region semiconductor strip and/or each source region semiconductor strip in each column of semiconductor stacked strip structure comprises a low-resistance conductive structure.
1 . A memory block, comprising:
a memory array, comprising: a plurality of columns of semiconductor stacked strip structures that are spaced apart along a row direction; wherein each column of stacked strip structure extends along a column direction and comprises at least one drain region semiconductor strip, at least one channel semiconductor strip, and at least one source region semiconductor strip that are stacked along a height direction;
each drain region semiconductor strip and/or each source region semiconductor strip in each column of semiconductor stacked strip structure comprises a low-resistance conductive structure;
each column of semiconductor stacked strip structure at a non-edge position comprises a first semiconductor substructure, a second semiconductor substructure, and an insulating isolation structure arranged between the first semiconductor substructure and the second semiconductor substructure;
each drain region semiconductor strip in the column of semiconductor stacked strip structure at the non-edge position is divided into a first drain region semiconductor sub-strip and a second drain region semiconductor sub-strip;
each channel semiconductor strip in the column of semiconductor stacked strip structure at the non-edge position is divided into a first channel semiconductor sub-strip and a second channel semiconductor sub-strip;
each source region semiconductor strip in the column of semiconductor stacked strip structure at the non-edge position is divided into a first source region semiconductor sub-strip and a second source region semiconductor sub-strip; and
each of the first drain region semiconductor sub-strip and the second drain region semiconductor sub-strip comprises a first drain region semiconductor layer structure, a second drain region semiconductor layer structure, and a third drain region semiconductor layer structure; the second drain region semiconductor layer structure is arranged between the first drain region semiconductor layer structure and the third drain region semiconductor layer structure; the first drain region semiconductor layer structure and the third drain region semiconductor layer structure are each of a silicon semiconductor layer structure, and the second drain region semiconductor layer structure is of a silicon germanium semiconductor layer structure; and/or
each of the first source region semiconductor sub-strip and the second source region semiconductor sub-strip comprises a first source region semiconductor layer structure, a second source region semiconductor layer structure, and a third source region semiconductor layer structure; the second source region semiconductor layer structure is arranged between the first source region semiconductor layer structure and the third source region semiconductor layer structure; the first source region semiconductor layer structure and the third source region semiconductor layer structure are each of a silicon semiconductor layer structure, and the second source region semiconductor layer structure is of a silicon germanium semiconductor layer structure.
2 . The memory block according to claim 1 , wherein,
the memory array comprises a plurality of memory cells distributed in a three-dimensional array; wherein the memory array comprises a plurality of memory subarray layers sequentially stacked along the height direction, and each memory subarray layer comprises a drain region semiconductor layer, a channel semiconductor layer, and a source region semiconductor layer stacked along the height direction;
in each memory subarray layer, the drain region semiconductor layer comprises a plurality of drain region semiconductor strips spaced apart along the row direction, each drain region semiconductor strip extending along the column direction; the channel semiconductor layer comprises a plurality of channel semiconductor strips spaced apart along the row direction, each channel semiconductor strip extending along the column direction; the source region semiconductor layer comprises a plurality of source region semiconductor strips spaced apart along the row direction, each source region semiconductor strip extending along the column direction;
the drain region semiconductor strips, the channel semiconductor strips, and the source region semiconductor strips that are in a same column are stacked to form a corresponding column of semiconductor stacked strip structure.
3 . The memory block according to claim 2 , wherein,
the column of semiconductor stacked strip structure is etched into a stepped structure at an edge position, for leading out each drain region semiconductor strip and each source region semiconductor strip in the column of semiconductor stacked strip structure.
4 . The memory block according to claim 2 , wherein,
adjacent two of the plurality of memory subarray layers comprise the drain region semiconductor layer, the channel semiconductor layer, the source region semiconductor layer, the channel semiconductor layer, and the drain region semiconductor layer, in a sequential cascade along the height direction, so as to share the same source region semiconductor layer;
an interlayer isolation layer is arranged on every adjacent two of the plurality of memory subarray layers to be isolated from another two of the plurality of memory subarray layers.
5 . The memory block according to claim 1 , wherein,
each drain region semiconductor strip and/or each source region semiconductor strip in each column of semiconductor stacked strip structure at a non-edge position comprises the low-resistance conductive structure.
6 . The memory block according to claim 1 , wherein,
a length of the second drain region semiconductor layer structure in the row direction is less than a length of the first drain region semiconductor layer structure and a length of the third drain region semiconductor layer structure in the row direction, to define a drain region filling space between the first drain region semiconductor layer structure, the second drain region semiconductor layer structure, and the third drain region semiconductor layer structure; a drain region low-resistance conductive layer structure is formed in the drain region filling space, and the low-resistance conductive structure in each of the first drain region semiconductor sub-strip and the second drain region semiconductor sub-strip comprises the drain region low-resistance conductive layer structure; and/or
a length of the second source region semiconductor layer structure in the row direction is less than a length of the first source region semiconductor layer structure and a length of the third source region semiconductor layer structure in the row direction, to define a source region filling space between the first source region semiconductor layer structure, the second source region semiconductor layer structure, and the third source region semiconductor layer structure; a source region low-resistance conductive layer structure is formed in the source region filling space, and the low-resistance conductive structure in each of the first source region semiconductor sub-stripe and the second source region semiconductor sub-strip comprises the source region low-resistance conductive layer structure.
7 . The memory block according to claim 6 , wherein,
the drain region low-resistance conductive layer structure and/or the source region low-resistance conductive layer structure is made of a high-conductivity material;
the drain region low-resistance conductive layer structure or the source region low-resistance conductive layer structure comprises a first conductive layer structure, a second conductive layer structure, a third conductive layer structure, a fourth conductive layer structure, and a fifth conductive layer structure; the first conductive layer structure is formed on a portion of an upper surface of the first drain region semiconductor layer structure or the first source region semiconductor layer structure, the second conductive layer structure is formed on a side of the second drain region semiconductor layer structure or the second source region semiconductor layer structure, the third conductive layer structure is formed on a portion of a lower surface of the third drain region semiconductor layer structure or the third source region semiconductor layer structure, the fourth conductive layer structure is formed on a side of the first drain region semiconductor layer structure or the first source region semiconductor layer structure, and the fifth conductive layer structure is formed on a side of the third drain region semiconductor layer structure or the third source region semiconductor layer; the first conductive layer structure, the second conductive layer structure, the third conductive layer structure, the fourth conductive layer structure, and the fifth conductive layer structure are made of a material comprising a metal silicide; or
the drain region low-resistance conductive layer structure or the source region low-resistance conductive layer structure comprises a first conductive layer structure, a second conductive layer structure, and a third conductive layer structure; the first conductive layer structure is formed on a portion of an upper surface of the first drain region semiconductor layer structure or the first source region semiconductor layer structure, the second conductive layer structure is formed on a side of the second drain region semiconductor layer structure or the second source region semiconductor layer structure, and the third conductive layer structure is formed on a portion of a lower surface of the third drain region semiconductor layer structure or the third source region semiconductor layer structure; each of the first conductive layer structure, the second conductive layer structure, and the third conductive layer structure comprises at least a first low-resistance layer; the first low-resistance layer is made of a material comprising titanium nitride or tantalum nitride; or
the drain region low-resistance conductive layer structure or the source region low-resistance conductive layer structure comprises a conductive layer structure filled in the drain region filling space or the source region filling space, and the conductive layer structure is made of a material comprising a metal.
8 . The memory block according to claim 7 , wherein,
each of the first conductive layer structure, the second conductive layer structure, and the third conductive layer structure further comprises a second low-resistance layer, wherein the second low-resistance layer is attached to a surface of the first low-resistance layer; a material of the second low-resistance layer comprises titanium or tantalum, or the material of the second low-resistance layer comprises a combination layer of titanium and another metal, or a combination layer of tantalum and another metal.
9 . The memory block according to claim 7 , wherein,
the first conductive layer structure and the third conductive layer structure are spaced apart from each other to define a first space configured to be filled with an insulating substance.