Memory device and storage device including the same
A memory chip performs phase calibration and duty cycle correction operations using first and second loop circuits. The first loop circuit includes a phase detector, a first counter, and a delay cell. The second loop circuit includes a phase generator, the phase detector, a second counter, and a duty correction circuit (DCC).
1 . A memory device, comprising:
a memory chip configured to perform a phase calibration operation and a duty cycle correction operation, during a training section, said memory chip comprising:
a first loop circuit, including:
a phase detector configured to generate a first comparison signal by detecting a phase difference between a first signal and a second signal, which are received from external the memory chip;
a first counter configured to generate a delay signal in response to the first comparison signal; and
a delay cell configured to perform the phase calibration operation on the first signal, in response to the delay signal; and
a second loop circuit, including:
a phase generator configured to generate a second reverse signal in response to the second signal;
the phase detector configured to generate a second comparison signal by comparing a duty cycle of a first reverse signal received from external the memory chip with a duty cycle of the second reverse signal;
a second counter configured to generate a control signal in response to the second comparison signal; and
a duty correction circuit (DCC) configured to perform the duty cycle correction operation on the second signal according to the control signal.
2 . The memory device of claim 1 , wherein the memory device is responsive to a clock signal, which operates as a read enable signal that toggles at a predetermined frequency during the training section.
3 . The memory device of claim 1 , wherein the first and second signals toggle at predetermined frequencies.
4 . The memory device of claim 3 , wherein the first and second signals correspond to data strobe signals.
5 . The memory device of claim 3 , wherein the first signal and the first reverse signal are out of phase from each other by 180 degrees; and wherein the second signal and the second reverse signal are out of phase from each other by 180 degrees.
6 . The memory device of claim 1 , wherein the memory chip is configured to sequentially perform the phase calibration operation and the duty cycle correction operation, in response to a DCC start command received from external the memory chip.
7 . The memory device of claim 1 , wherein the first loop circuit is configured to: detect the phase difference between the first signal and the second signal, generate the first comparison signal, generate the delay signal according to the first comparison signal, adjust a delay time of the first signal, and align phases of the first signal and the second signal.
8 . The memory device of claim 1 , wherein the second loop circuit is configured to: detect a phase difference between the first reverse signal and the second reverse signal, generate the second comparison signal, generate the control signal according to the second comparison signal, and perform the duty cycle correction operation to thereby adjust a duty cycle of the second signal.
9 . A storage device, comprising:
a controller configured to provide a first signal, a second signal, and a first reverse signal; and
a memory device configured to perform a phase calibration operation and a duty cycle correction operation, said memory device comprising:
a phase detector configured to detect a phase difference between the first signal and the second signal;
a first counter configured to generate a delay signal, based on the phase difference;
a delay cell configured to receive the delay signal and perform a phase calibration operation on the first signal;
a phase generator configured to generate a second reverse signal, based on the second signal;
a second counter configured to, based on a difference generated by comparing a duty cycle of the first reverse signal with a duty cycle of the second reverse signal, generate a control signal; and
a duty correction circuit (DCC) configured to receive the control signal and perform a duty cycle correction operation on the second signal.
10 . The storage device of claim 9 ,
wherein the memory device comprises a plurality of memory chips; and
wherein the memory device is electrically connected to the controller through a plurality of input and output pins including a first pin and a second pin, and is configured to receive a clock signal through the first pin and receive the first signal, the first reverse signal, and the second signal through the second pin.
11 . The storage device of claim 10 , wherein the clock signal is a read enable signal that toggles at a predetermined frequency during a training section.
12 . The storage device of claim 9 , wherein the first and second signals toggle at predetermined frequencies.
13 . The storage device of claim 12 , wherein the first and second signals correspond to data strobe signals.
14 . The storage device of claim 9 , wherein the memory device is configured to sequentially perform the phase calibration operation and the duty cycle correction operation, in response to a DCC start command received from the controller.
15 . The storage device of claim 14 , wherein the memory device is configured to:
generate a first comparison signal by detecting a phase difference between the first signal and the second signal;
generate the delay signal according to the first comparison signal; and
adjust a delay time of the first signal to align phases of the first signal and the second signal.
16 . The storage device of claim 14 , wherein the memory device is configured to:
generate a second comparison signal by detecting a phase difference between the first reverse signal and the second reverse signal;
generate the control signal according to the second comparison signal; and
perform the duty cycle correction operation to adjust a duty cycle of the second signal.
17 . A memory device, comprising:
a plurality of memory chips; and
an interface chip configured to perform communication between a controller and the plurality of memory chips;
wherein the interface chip comprises a first loop circuit configured to perform a phase calibration operation during a training section of the controller, and a second loop circuit configured to perform a duty cycle correction operation during the training section of the controller;
wherein the first loop circuit comprises:
a phase detector configured to detect a phase difference between a first signal and a second signal, which are received from the controller, and generate a first comparison signal;
a first counter configured to generate a delay signal, based on the first comparison signal; and
a delay cell configured to perform the phase calibration operation on the first signal according to the delay signal; and
wherein the second loop circuit comprises:
a phase generator configured to generate a second reverse signal based on the second signal;
the phase detector configured to compare a duty cycle of a first reverse signal received from the controller with a duty cycle of the second reverse signal and generate a second comparison signal;
a second counter configured to generate a control signal, based on the second comparison signal; and
a duty correction circuit (DCC) configured to perform the duty cycle correction operation on the second signal according to the control signal.
18 . The memory device of claim 17 , wherein the memory device is responsive to a clock signal, which operates as a read enable signal that toggles at a predetermined frequency during the training section; and wherein the first and second signals correspond to data strobe signals that toggle at predetermined frequencies.
19 . The memory device of claim 17 , wherein the interface chip is configured to sequentially perform the phase calibration operation and the duty cycle correction operation, in response to a DCC start command received from the controller.
20 . The memory device of claim 17 ,
wherein the first loop circuit is configured to:
detect the phase difference between the first signal and the second signal and generate the first comparison signal;
generate the delay signal according to the first comparison signal; and
align phases of the first signal and the second signal by adjusting a delay time of the first signal; and
wherein the second loop circuit is configured to:
generate the second comparison signal by detecting a phase difference between the first reverse signal and the second reverse signal;
generate the control signal according to the second comparison signal; and
perform the duty cycle correction operation to adjust a duty cycle of the second signal.