IP Library › Granted Patent US 12,750,161
Granted Patent B2
US 12,750,161 · App. 18/661,632 · Granted Sep 29, 2026

Apparatus for transmitting and receiving signal

Inventors: Soonwoo Choi (Suwon-si, KR); Minki Ahn (Suwon-si, KR); Junyoung Jeong (Suwon-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H04L1/0045H03M13/3927H04L25/0258H04L27/38
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Quick Facts
Patent No.
US 12,750,161
App. No.
18/661,632
Granted
Sep 29, 2026
Kind
B2
Abstract

An apparatus for transmitting and receiving signal may include a transceiver configured to receive a reception signal through a channel and demodulate the reception signal into a reception symbol and a channel estimation value corresponding to the reception signal, and a demapper configured to detect a modulation type of the reception signal, calculate a first status data based on a first value obtained by zero-forcing the reception symbol and a second value obtained by squaring the channel estimation value, calculate a second status data based on the second value, and estimate bit information with respect to the reception symbol based on the modulation type, the first status data, and the second status data.

Claims (96)

1 . An apparatus for transmitting and receiving signal, the apparatus comprising:

a transceiver configured to receive a reception signal through a channel and demodulate the reception signal into a reception symbol and a channel estimation value corresponding to the reception signal; and

a demapper configured to:

detect a modulation type of the reception signal,

calculate a first status data based on a first value obtained by zero-forcing the reception symbol and a second value obtained by squaring the channel estimation value,

calculate a second status data based on the second value, and

estimate bit information with respect to the reception symbol based on the modulation type, the first status data, and the second status data, wherein:

the bit information comprises a log likelihood ratio (LLR) signal of n bits,

the LLR signal comprises a plurality of first bits representing a real part and a plurality of second bits representing an imaginary part, and

the demapper comprises an LLR calculator configured to determine the LLR signal by using a piecewise linear function representing the reception symbol as a plurality of linear functions by dividing the reception symbol into a plurality of sections and approximating each of the plurality of sections by a linear function.

2 . The apparatus of claim 1 , wherein:

the LLR calculator is further configured to determine the LLR signal by using an approximation function that approximates the reception symbol with respect to each of the plurality of first bits and the plurality of second bits.

3 . The apparatus of claim 2 , wherein:

the LLR calculator comprises a plurality of selectors configured to output one of an absolute value of the first status data and outputs of a plurality of calculation units based on the modulation type,

each of the plurality of calculation units comprises an absolute value detector and an adder connected to the absolute value detector and is configured to subtract an output of the absolute value detector from a value obtained by multiplying the second status data and a corresponding one among a plurality of constants,

a first absolute value detector of a first calculation unit among the plurality of calculation units is configured to receive the first status data, and

a corresponding one among the plurality of selectors is configured to output a signal to the absolute value detector of a remaining calculation unit excluding the first calculation unit from the plurality of calculation units.

4 . The apparatus of claim 3 , wherein:

the plurality of calculation units includes the first calculation unit and second to fifth calculation units,

the first calculation unit corresponds to a first constant of 2 5 ,

the second calculation unit corresponds to a second constant of 2 4 ,

the third calculation unit corresponds to a third constant of 2 3 ,

the fourth calculation unit corresponds to a fourth constant of 2 2 , and

the fifth calculation unit corresponds to a fifth constant of 2 1 .

5 . The apparatus of claim 4 , wherein the LLR calculator is configured to determine the LLR signal based on outputs of the first to fifth calculation units.

6 . The apparatus of claim 4 , wherein the LLR calculator further comprises:

a lookup table containing mapping of outputs of the first to fifth calculation units to each of the plurality of first bits or each of the plurality of second bits depending on the modulation type.

7 . The apparatus of claim 1 , wherein the LLR calculator comprises:

a slicer configured to detect a section corresponding to the reception symbol based on the first status data and the second status data;

a coefficient lookup table storing information about a first coefficient corresponding to the first status data and a second coefficient corresponding to the second status data depending on the section;

a first multiplier configured to generate a first output by multiplying the second status data and the second coefficient;

a first adder configured to generate a second output by adding the first output and the first status data; and

a second multiplier configured to determine the LLR signal by multiplying the second output and the first coefficient.

8 . The apparatus of claim 7 , wherein:

the slicer comprises:

an absolute value detector configured to receive the first status data;

a clipper configured to receive an output of the absolute value detector and clip the output of the absolute value detector based on the modulation type and the second status data; and

a plurality of calculation units,

each of the plurality of calculation units comprises:

an adder configured to subtract a value obtained by multiplying the second status data and a corresponding one among a plurality of constants from a corresponding input; and

a selector connected to the adder and configured to output one of the corresponding input and an output of the adder based on a sign of the output of the adder,

a first adder of a first calculation unit among the plurality of calculation units connected to the clipper is configured to receive an output of the clipper,

a first selector of the first calculation unit is configured to output one of the output of the first adder and the output of the clipper, and

a corresponding selector of the plurality of calculation units is configured to output a signal to an adder of a remaining calculation unit excluding the first calculation unit from the plurality of calculation units.

9 . The apparatus of claim 8 , wherein:

the plurality of calculation units includes the first calculation unit and second to fourth calculation units,

the first calculation unit corresponds to a first constant of 2 5 ,

the second calculation unit corresponds to a second constant of 2 4 ,

the third calculation unit corresponds to a third constant of 2 3 ,

the fourth calculation unit corresponds to a fourth constant of 2 2 , and

the slicer further comprises a fifth adder connected to an output of the fourth calculation unit, and the fifth adder configured to subtract a value obtained by multiplying 2 1 and the second status data from the output of the fourth calculation unit.

10 . The apparatus of claim 1 , wherein the LLR calculator comprises:

a slicer configured to detect a section corresponding to the reception symbol based on the first status data and the second status data;

a coefficient lookup table storing information about a first coefficient corresponding to the first status data and a second coefficient corresponding to the second status data depending on the section;

a first multiplier configured to generate a first output by multiplying the first coefficient and the first status data;

a second multiplier configured to generate a second output by multiplying the second status data and the second coefficient; and

a first adder configured to determine the LLR signal by adding the first output and the second output.

11 . The apparatus of claim 1 , wherein:

the LLR signal is determined by using an approximation function that approximates the reception symbol with respect to a portion of the plurality of first bits and a portion of the plurality of second bits, and

the LLR signal is determined by using the piecewise linear function that approximates the reception symbol with respect to a remaining first bit excluding the portion of the plurality of first bits and a remaining second bit excluding the portion of the plurality of second bits.

12 . The apparatus of claim 1 , wherein:

the first status data is Z·A|H| 2 , wherein Z is a result of zero-forcing the reception symbol, A is a normalization constant, and His the channel estimation value of the channel, and

the second status data is a A·A|H| 2 .

13 . An operation method of an apparatus for transmitting and receiving signal, the operation method comprising:

receiving a reception signal through a channel and demodulating the reception signal into a reception symbol and a channel estimation value corresponding to the reception signal;

detecting a modulation type of the reception signal;

calculating a first status data based on a first value obtained by zero-forcing the reception symbol and a second value obtained by squaring the channel estimation value;

calculating a second status data based on the second value;

estimating bit information with respect to the reception symbol based on the modulation type, the first status data, and the second status data; and

performing decryption on the bit information,

wherein the estimating of the bit information comprises:

determining a log likelihood ratio (LLR) signal, which comprises a plurality of first bits representing a real part and a plurality of second bits representing an imaginary part, by using a piecewise linear function representing the reception symbol as a plurality of linear functions by dividing the reception symbol into a plurality of sections and approximating each of the plurality of sections by a linear function.

14 . The operation method of claim 13 , wherein the estimating of the bit information further comprises:

determining the LLR signal by using an approximation function that approximates the reception symbol with respect to each of the plurality of first bits and the plurality of second bits.

15 . The operation method of claim 13 , wherein the estimating of the bit information further comprises:

determining the LLR signal by using an approximation function that approximates the reception symbol with respect to a portion of the plurality of first bits and a portion of the plurality of second bits; and

determining the LLR signal by using the piecewise linear function with respect to a remaining first bit excluding the portion of the plurality of first bits and a remaining second bit excluding the portion of the plurality of second bits.

16 . An apparatus for transmitting and receiving signal, the apparatus comprising:

a transceiver configured to receive a reception signal through a channel and demodulate the reception signal into a reception symbol and a channel estimation value corresponding to the reception signal;

a status data calculator configured to detect a modulation type of the signal, calculate a first status data based on a first value obtained by zero-forcing the reception symbol and a second value obtained by squaring the channel estimation value, and calculate a second status data based on the second value;

an LLR calculator configured to estimate a log likelihood ratio (LLR) signal of n bits comprising a plurality of first bits representing a real part and a plurality of second bits representing an imaginary part with respect to the reception symbol based on the modulation type, the first status data, and the second status data; and

a lookup table storing a mapping relationship between the reception symbol and the plurality of first bits or the plurality of second bits depending on the modulation type,

wherein the LLR calculator is further configured to determine the LLR signal by using a piecewise linear function representing the reception symbol as a plurality of linear functions by dividing the reception symbol into a plurality of sections and approximating each of the plurality of sections by a linear function.

17 . The apparatus of claim 16 , wherein:

the LLR calculator is configured to further determine the LLR signal by using an approximation function that approximates the reception symbol with respect to each of the plurality of first bits and the plurality of second bits,

the LLR calculator comprises a plurality of selectors configured to output one of an absolute value of the first status data and outputs of a plurality of calculation units based on the modulation type,

each of the plurality of calculation units comprises an absolute value detector and an adder connected to the absolute value detector and is configured to subtract an output of the absolute value detector from a value obtained by multiplying the second status data and a corresponding one among a plurality of constants,

a first absolute value detector of a first calculation unit among the plurality of calculation units is configured to receive the first status data, and

a corresponding one among the plurality of selectors is configured to output a signal to the absolute value detector of a remaining calculation unit excluding the first calculation unit from the plurality of calculation units.

18 . The apparatus of claim 16 , wherein:

the LLR calculator comprises:

a slicer configured to detect a section corresponding to the reception symbol based on the first status data and the second status data;

a coefficient lookup table storing information about a first coefficient corresponding to the first status data and a second coefficient corresponding to the second status data depending on the section;

a first multiplier configured to generate a first output by multiplying the second status data and the second coefficient;

a first adder configured to generate a second output by adding the first output and the first status data; and

a second multiplier configured to determine the LLR signal by multiplying the second output and the first coefficient.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2024
From: CHOI, SOONWOO; AHN, MINKI; JEONG, JUNYOUNG
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 067531/0686 →
Priority Claims (2)
KR 10-2023-0078203 · Jun 19, 2023 · national
KR 10-2023-0122746 · Sep 14, 2023 · national
Continuity (1)
Related Publication 20240421935A1 · Dec 19, 2024
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