Transistor device including a plurality of nanostructure channels and methods of formation with continuous polysilicon on diffusion edge (CPODE) process

1 . A method, comprising:

forming, over a semiconductor substrate, a plurality of nanostructure layers in a direction that is perpendicular to the semiconductor substrate,

wherein the plurality of nanostructure layers comprises a plurality of sacrificial layers alternating with a plurality of channel layers;

forming, over the plurality of nanostructure layers, a dummy gate structure;

removing portions of the plurality of nanostructure layers to form one or more recesses adjacent to one or more sides of the dummy gate structure;

forming one or more source/drain regions in the one or more recesses;

replacing, after forming the one or more source/drain regions, the dummy gate structure and portions of the sacrificial layers under the dummy gate structure with a metal gate structure,

wherein the metal gate structure wraps around at least three sides of the channel layers;

removing, to form an active region isolation recess after replacing the dummy gate structure and the portions of the sacrificial layers under the dummy gate structure with the metal gate structure:

a portion of the metal gate structure,

portions of the channel layers around which the metal gate structure wraps, and

a mesa region, under the portions of the channel layers, that extends above the semiconductor substrate; and

forming an active region isolation structure in the active region isolation recess.

2 . The method of claim 1 , further comprising:

removing, prior to removing the portion of the metal gate structure to form the active region isolation recess, another portion of the metal gate structure to form a gate isolation recess in the metal gate structure; and

forming, prior to removing the portion of the metal gate structure to form the active region isolation recess, a gate isolation structure in the gate isolation recess.

3 . The method of claim 2 , wherein removing the portion of the metal gate structure, the portions of the channel layers around which the metal gate structure wraps, and the mesa region comprises:

removing, based on the gate isolation structure, the portion of the metal gate structure, the portions of the channel layers around which the metal gate structure wraps, and the mesa region.

4 . The method of claim 1 , further comprising:

removing, prior to removing the portion of the metal gate structure to form the active region isolation recess, a plurality of other portions of the metal gate structure to form a plurality of gate isolation recesses in the metal gate structure; and

forming, prior to removing the portion of the metal gate structure to form the active region isolation recess, a plurality of gate isolation structures in the plurality of gate isolation recesses.

5 . The method of claim 4 , wherein removing the portion of the metal gate structure, the portions of the channel layers around which the metal gate structure wraps, and the mesa region comprises:

removing, from between the plurality of gate isolation structures, the portion of the metal gate structure, the portions of the channel layers around which the metal gate structure wraps, and the mesa region.

6 . The method of claim 5 , wherein forming the active region isolation structure comprises:

forming a dielectric liner on sidewalls of the plurality of gate isolation structures in the active region isolation recess; and

filling the active region isolation recess with a dielectric layer over the dielectric liner.

7 . The method of claim 4 , wherein forming the plurality of gate isolation structures comprises:

forming the plurality of gate isolation structures such that the plurality of gate isolation structures extend in a first direction across the metal gate structure; and

wherein forming the active region isolation structure comprises:

forming the active region isolation structure such that the active region isolation structure extends in a second direction in which the metal gate structure extends.

8 . A method, comprising:

forming, over a semiconductor substrate, a plurality of nanostructure layers in a direction that is perpendicular to the semiconductor substrate,

wherein the plurality of nanostructure layers comprises a plurality of sacrificial layers alternating with a plurality of channel layers;

forming, over the plurality of nanostructure layers, a plurality of dummy gate structures;

removing portions of the plurality of nanostructure layers to form one or more recesses adjacent to one or more sides of a dummy gate structure of the plurality of dummy gate structures;

forming one or more source/drain regions in the one or more recesses;

replacing, after forming the one or more source/drain regions, the plurality of dummy gate structures and portions of the sacrificial layers under the plurality of dummy gate structures with a plurality of metal gate structures,

wherein the plurality of metal gate structures wraps around the channel layers;

forming gate isolation structures across the plurality of metal gate structures after replacing the dummy gate structure and the portions of the sacrificial layers under the dummy gate structure with the metal gate structure;

removing, between the gate isolation structures to form an active region isolation recess:

a portion of a metal gate structure of the plurality of metal gate structures,

portions of the channel layers around which the metal gate structure wraps, and

a mesa region, under the portions of the channel layers, that extends above the semiconductor substrate; and

forming an active region isolation structure in the active region isolation recess between the gate isolation structures.

9 . The method of claim 8 , wherein removing the portion of the metal gate structure, the portions of the channel layers around which the metal gate structure wraps, and the mesa region comprises:

etching, using the gate isolation structures as a self-aligned mask, the portion of the metal gate structure, the portions of the channel layers around which the metal gate structure wraps, and the mesa region.

10 . The method of claim 8 , wherein removing the portion of the metal gate structure, the portions of the channel layers around which the metal gate structure wraps, and the mesa region comprises:

performing a first etch operation to remove the portion of the metal gate structure; and

performing, after the first etch operation, a second etch operation to remove the portions of the channel layers around which the metal gate structure wraps, and the mesa region.

11 . The method of claim 10 , further comprising:

performing, prior to the first etch operation, a third etch operation to remove a portion of a hard mask layer over the portion of the metal gate structure.

12 . The method of claim 11 , further comprising:

forming the hard mask layer over the gate isolation structures prior to removing the portion of the metal gate structure, the portions of the channel layers around which the metal gate structure wraps, and the mesa region.

13 . The method of claim 8 , wherein forming the active region isolation structure comprises:

forming a dielectric liner in the active region isolation recess; and

filling the active region isolation recess with a dielectric layer over the dielectric liner.

14 . The method of claim 13 , wherein forming the dielectric liner comprises:

forming the dielectric liner such that the dielectric liner is in direct contact with sidewalls of the gate isolation structures.

15 . A semiconductor device, comprising:

a first plurality of nanostructure channels over a first mesa region that extends above a semiconductor substrate,

wherein the first plurality of nanostructure channels are arranged in a direction that is perpendicular to the semiconductor substrate;

a second plurality of nanostructure channels over a second mesa region that extends above the semiconductor substrate,

wherein the second plurality of nanostructure channels are arranged in the direction that is perpendicular to the semiconductor substrate;

a first metal gate structure wrapping around each of the first plurality of nanostructure channels;

a second metal gate structure wrapping around each of the second plurality of nanostructure channels;

a gate isolation structure between the first metal gate structure and the second metal gate structure; and

an active region isolation structure between the gate isolation structure and the second metal gate structure,

wherein a dielectric liner of the active region isolation structure is included directly on a sidewall of the gate isolation structure, and

wherein the first metal gate structure is in direct contact with another sidewall of the gate isolation structure.

16 . The semiconductor device of claim 15 , further comprising:

another gate isolation structure between the active region isolation structure and the second metal gate structure.

17 . The semiconductor device of claim 16 , wherein the second metal gate structure is in direct contact with a sidewall of the other gate isolation structure.

18 . The semiconductor device of claim 17 , wherein the dielectric liner of the active region isolation structure is in direct contact with another sidewall of the other gate isolation structure.

19 . The semiconductor device of claim 15 , wherein the dielectric liner is between a dielectric layer of the active region isolation structure and the gate isolation structure.

20 . The semiconductor device of claim 15 , wherein the active region isolation structure is configured to create electrical isolation between the first plurality of nanostructure channels and the second plurality of nanostructure channels.