Semiconductor devices and methods of manufacture
Semiconductor devices using a dielectric structure and methods of manufacturing are described herein. The semiconductor devices are directed towards gate-all-around (GAA) devices that are formed over a substrate and are isolated from one another by the dielectric structure. The dielectric structure is formed over the fin between two GAA devices and cuts a gate electrode that is formed over the fin into two separate gate electrodes. The two GAA devices are also formed with bottom spacers underlying source/drain regions of the GAA devices. The bottom spacers isolate the source/drain regions from the substrate. The dielectric structure is formed with a shallow bottom that is located above the bottoms of the bottom spacers.
1. A semiconductor device comprising:
a first nanostructure and a second nanostructure overlying a fin over a semiconductor substrate;
an isolation region adjacent the fin;
a first inner spacer located between the first nanostructure and the semiconductor substrate;
a first spacer material in contact with the first inner spacer;
a first source/drain region over an upper surface of the first spacer material, wherein the first source/drain region contacts both the first spacer material and the first inner spacer;
a first gate electrode surrounding the first nanostructure and the second nanostructure;
a second gate electrode adjacent the first gate electrode and having a longitudinal axis parallel to a longitudinal axis of the first gate electrode; and
a dielectric structure extending through the second gate electrode and into the fin, a bottommost surface of the dielectric structure being above a bottom of the first spacer material, the dielectric structure comprising:
a first layer having a bottom surface on a top surface of the isolation region; and
a second layer adjacent the first layer, the second layer extending into the fin.
2. The semiconductor device of claim 1 , wherein the first spacer material has a height of between about 3 nm and about 30 nm.
3. The semiconductor device of claim 1 , wherein a length of an interface between the first spacer material and the first inner spacer is between about 3 nm and about 15 nm.
4. The semiconductor device of claim 1 , wherein the dielectric structure extends into the fin between about 2 nm and about 20 nm.
5. The semiconductor device of claim 1 , wherein the first spacer material comprises silicon oxide.
6. The semiconductor device of claim 1 , wherein the first spacer material comprises silicon oxynitride.
7. The semiconductor device of claim 1 , wherein the first inner spacer has a height of between about 5 nm and about 20 nm.
8. A semiconductor device comprising:
a first bottom spacer separating a first source/drain region from a semiconductor substrate;
a first inner spacer in contact with the first bottom spacer and the first source/drain region;
a first nanostructure in contact with both the first inner spacer and the first source/drain region;
a second nanostructure overlying the first nanostructure;
a gate electrode surrounding both the first nanostructure and the second nanostructure, wherein the first inner spacer extends lower than an upper surface of the semiconductor substrate below the first nanostructure; and
a dielectric structure adjacent to the first source/drain region, the first source/drain region being between the gate electrode and the dielectric structure, the dielectric structure having a bottommost surface further from the semiconductor substrate than the first bottom spacer.
9. The semiconductor device of claim 8 , wherein the first inner spacer has a width of between about 2 nm and about 10 nm.
10. The semiconductor device of claim 9 , wherein the first inner spacer has a height of between about 5 nm and about 20 nm.
11. The semiconductor device of claim 10 , further comprising a second inner spacer separated from the first inner spacer by a first spacing of between about 3 nm and about 10 nm.
12. The semiconductor device of claim 8 , wherein the first nanostructure has a first channel length of between about 5 nm and about 180 nm.
13. The semiconductor device of claim 8 , wherein the first nanostructure has a first channel width of between about 8 nm and about 100 nm.
14. The semiconductor device of claim 8 , wherein the first inner spacer is in physical contact with a first side and a second side of the first nanostructure, the first side being at an angle to the second side.
15. A semiconductor device comprising:
a stack of nanostructures over a first semiconductor fin, the first semiconductor fin being located over a substrate;
an isolation region extending between the first semiconductor fin and a second semiconductor fin located over the substrate, the isolation region having a first surface facing away from the substrate, the first surface being located a first distance away from the substrate;
a first source/drain region adjacent the stack of nanostructures;
a gate electrode surrounding each nanostructure within the stack of nanostructures;
a dielectric structure adjacent to the gate electrode, the dielectric structure having a first bottommost surface and a first portion located adjacent to the second semiconductor fin, the first portion being located a second distance away from the substrate, the second distance being less than the first distance; and
a first bottom spacer vertically separating the first source/drain region from the substrate, the first bottom spacer having a second bottom surface, the second bottom surface being lower than the first bottommost surface.
16. The semiconductor device of claim 15 , wherein the second distance is at most 20 nm less than the first distance.
17. The semiconductor device of claim 15 , further comprising:
an inner spacer adjacent the first bottom spacer and separating the first bottom spacer from the gate electrode.
18. The semiconductor device of claim 17 , wherein the inner spacer has a first interface with the first bottom spacer, the first interface having a distance of between about 3nm and about 15 nm.
19. The semiconductor device of claim 18 , wherein the inner spacer has a first height of between about 5 nm and about 20 nm.
20. The semiconductor device of claim 19 , wherein the first height is greater than a second height of the gate electrode.