IP Library › Granted Patent US 12,751,276
Granted Patent B2
US 12,751,276 · App. 18/603,487 · Granted Sep 29, 2026

Interconnect structure with intra-level metal line connectors

Inventors: James P Mazza (Saratoga Springs, NY); Nicholas Anthony Lanzillo (Wynantskill, NY); Reinaldo Vega (Mahopac, NY); David Wolpert (Poughkeepsie, NY); Takashi Ando (Eastchester, NY)
Assignee: International Business Machines Corporation
H10W20/432H10W20/081H10W20/435H10W20/063
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Quick Facts
Patent No.
US 12,751,276
App. No.
18/603,487
Granted
Sep 29, 2026
Kind
B2
Abstract

A semiconductor interconnect structure and formation thereof. The semiconductor interconnect structure includes a first metal line, a second metal line, and a third metal line running along a first orientation within a metal level, where the second metal line is located between the first and third metal lines. The semiconductor interconnect structure further includes a metal line connector running along a second orientation within the metal level. The metal line connector is located below the second metal line, and connected to the first and third metal lines.

Claims (38)

1 . A semiconductor interconnect structure, comprising:

a first metal line, a second metal line, and a third metal line running along a first orientation within a metal level, wherein the second metal line is located between the first and third metal lines; and

a metal line connector running along a second orientation within the metal level, wherein the metal line connector is located below the second metal line, and connected to the first and third metal lines.

2 . The semiconductor interconnect structure of claim 1 , further comprising:

an insulating material that isolates the second metal line from the first metal line, the third metal line, and the metal line connector.

3 . The semiconductor interconnect structure of claim 1 , wherein the second orientation is orthogonal to the first orientation.

4 . The semiconductor interconnect structure of claim 1 , wherein:

the first metal line, the third metal line, and the metal line connector are formed using a subtractive manufacturing process; and

the second metal line is formed using an additive manufacturing process.

5 . The semiconductor interconnect structure of claim 1 , wherein:

the first metal line and the third metal line are subtractively etched metal lines; and

the second metal line is a damascene metal line.

6 . The semiconductor interconnect structure of claim 1 , wherein:

a bottom surface of the metal line connector is substantially coplanar with a bottom surface of the first and third metal lines; and

a top surface of the metal line connector is located below a top surface of the first and third metal lines.

7 . The semiconductor interconnect structure of claim 1 , wherein:

a top surface of the second metal line is substantially coplanar with a top surface of the first and third metal lines; and

a bottom surface of the second metal line is located above a top surface of the metal line connector.

8 . The semiconductor interconnect structure of claim 1 , wherein a first height of the first and third metal lines is greater than a second height of the second metal line.

9 . A semiconductor interconnect structure, comprising:

a first metal line, a second metal line, and a third metal line running along a first orientation within a metal level, wherein the second metal line is located between the first and third metal lines; and

a metal line connector running along a second orientation within the metal level, wherein the metal line connector is located above the second metal line, and connected to the first and third metal lines.

10 . The semiconductor interconnect structure of claim 9 , further comprising:

an insulating material that isolates the second metal line from the first metal line, the third metal line, and the metal line connector.

11 . The semiconductor interconnect structure of claim 9 , wherein the second orientation is orthogonal to the first orientation.

12 . The semiconductor interconnect structure of claim 9 , wherein:

the first metal line, the third metal line, and the metal line connector are formed using an additive manufacturing process; and

the second metal line is formed using a subtractive manufacturing process.

13 . The semiconductor interconnect structure of claim 9 , wherein:

the first metal line and the third metal line are damascene metal lines; and

the second metal line is a subtractively etched metal line.

14 . The semiconductor interconnect structure of claim 9 , wherein:

a top surface of the metal line connector is substantially coplanar with a top surface of the first and third metal lines; and

a bottom surface of the metal line connector is located above a bottom surface of the first and third metal lines.

15 . The semiconductor interconnect structure of claim 9 , wherein:

a bottom surface of the first and third metal lines is substantially coplanar with a bottom surface of the second metal line; and

a top surface of the second metal line is located below a bottom surface of the metal line connector.

16 . The semiconductor interconnect structure of claim 9 , wherein a first height of the first and third metal lines is greater than a second height of the second metal line.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2024
From: MAZZA, JAMES P; LANZILLO, NICHOLAS ANTHONY; VEGA, REINALDO; WOLPERT, DAVID; ANDO, TAKASHI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 066749/0818 →
Continuity (1)
Related Publication 20250293145A1 · Sep 18, 2025
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