Method of producing a semiconductor component having a compliant buffer layer
A method for producing a semiconductor component with the following steps. A semiconductor chip is provided having electrical contacts in a contact making region. A housing including a rear plate and a side area is provided and surrounds the semiconductor chip. A first compliant buffer layer is applied on a rear plate. The semiconductor chip is applied to the first compliant buffer layer, and a second compliant buffer layer is applied to and around the semiconductor chip except in the contact making region. A contact passage plate is provided with an opening over the contact areas and the contact passage plate is fixed to the second compliant buffer layer.
1. A method for producing a semiconductor component, the method comprising
providing a semiconductor chip having electrical contacts in a contact making region,
providing a housing that surrounds the semiconductor chip, the housing having a rear plate and a side area,
applying a first compliant buffer layer on the rear plate,
applying the semiconductor chip to the first compliant buffer layer,
applying a second compliant buffer layer to and around the semiconductor chip, except in the contact making region,
providing a contact passage plate having an opening over the contact making region, and
fixing the contact passage plate to the second compliant buffer layer.
2. The method of claim 1 , further comprising forming a unitary frame structure in which the side area and the rear plate are integral with each other.
3. The method of claim 1 , further comprising forming the side area on the rear plate after applying the semiconductor chip to the first compliant buffer layer.
4. The method of claim 3 , wherein forming the side area comprises casting material between a boundary area and the first compliant buffer layer.
5. The method of claim 1 , further comprising producing a plurality of semiconductor components simultaneously on a mounting plate that includes a plurality of rear plates, and separating the rear plates.
6. The method of claim 5 , further comprising selecting the mounting plate to include the spatial extent of a wafer.
7. The method of claim 1 , further comprising forming a boundary area from a side of at least one of the first and the second compliant buffer layers of an adjacent semiconductor component.
8. The method of claim 1 , further comprising applying a third compliant buffer layer within the contact making region between the electrical contacts.
9. The method of claim 1 , further comprising providing material in the opening of the contact passage plate.
10. The method of claim 1 , further comprising selecting the opening in the contact passage plate to be larger than the opening in the second compliant buffer layer.
11. The method of claim 1 , further comprising selecting a material for the housing from a group consisting of polymerplastic, ceramic, glass, epoxy resin and metal.
12. The method of claim 1 , further comprising selecting a spacing between the semiconductor chip and the side wall proportional to a solder thickness.
13. The method of claim 1 , further comprising selecting a spacing between the semiconductor chip and the side wall proportional to a ratio of the difference between a thermal expansion coefficient of the housing and a thermal expansion coefficient of the semiconductor chip and the difference between a thermal expansion coefficient of the first and the second buffer layers and a thermal expansion coefficient of the housing.
14. The method of claim 1 , further comprising applying conductive bumps to the semiconductor component for electrical contacts.
15. The method of claim 14 , further comprising selecting the conductive bumps to include solder.
16. The method of claim 15 , further comprising selecting the conductive bumps to include silicone bumps having electrical conduction areas.
17. The method of claim 1 , further comprising selecting packaging for the semiconductor component from a group consisting of: a wafer level package, a flip chip, and a chip scale package.
18. The method of claim 1 , further comprising selecting a material for the first and the second buffer layers such that a thermal expansion coefficient of the first and the second buffer layers is greater than a thermal expansion of a printed circuit board material.
19. The method of claim 1 , further comprising selecting a thermally conductive material for at least one of the first and the second buffer layers.
20. The method of claim 1 , further comprising selecting a highly elastic material for at least one of the first and the second buffer layers.
21. The method of claim 1 , further comprising choosing a material of the housing such that a thermal expansion coefficient of the housing is equal to that of a printed circuit board material.
22. The method of claim 1 , further comprising selecting a material of the housing such that a thermal expansion coefficient of the housing is greater than a thermal expansion coefficient of the semiconductor chip.
23. The method of claim 22 , further comprising selecting at least one of the first and the second buffer layers to include a foamed material.
24. The method of claim 1 , further comprising selecting a material such that a thermal expansion coefficient of the first and the second buffer layers and a thermal expansion coefficient of the semiconductor chip is equal to a thermal expansion coefficient of the housing and a thermal expansion coefficient the printed circuit board material.
25. The method of claim 1 , further comprising selecting at least one of the first and the second buffer layers to include a polymer.
26. A semiconductor component, produced by the method of claim 1 .