IP Library Granted Patent US 6,963,213
Granted Patent B1
US 6,963,213 · App. 10/710,670 · Granted Nov 8, 2005

Auto-recovery wafer testing apparatus and wafer testing method

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,963,213
App. No.
10/710,670
Granted
Nov 8, 2005
Kind
B1
Abstract

Auto-recovery wafer testing apparatus and wafer testing method are provided. The wafer testing apparatus includes a main system, a tester and a real-time accessing module. The main system controls the process of the wafer testing. The tester is electrically coupled to the main system for receiving commands from the main system to perform testing on a plurality of chips sequentially and output the testing data correspondingly. The real-time accessing module is electrically coupled to the tester for simultaneously accessing the testing data. In an event when the testing is accidentally interrupted, the tester can produce auto-recovery data according to the testing data saved in the real-time accessing module, and continue testing, based on the auto-recovery data, from the chip being last but incompletely tested. The use of the wafer testing apparatus and method can save testing time and enhance the production efficiency.

Claims (10)

1. An auto-recovery wafer testing method, comprising:

a first testing step to test sequentially a plurality of chips on a wafer and spontaneously save testing data for each of the chips;

an auto-recovery data generating step, wherein, if the first testing step is accidentally interrupted, auto-recovery data are generated based on the testing data that is saved; and

a second testing step for continuing the testing, based on the auto-recovery data, from a chip being last but incompletely tested.

2. The wafer testing method as recited in claim 1 , wherein, during the first testing step, a first testing unit is used to test the chips and output corresponding testing data for each of the chips.

3. The wafer testing method as recited in claim 1 , wherein, during the first testing step, a real-time accessing module is used to instantaneously save testing data for each of the chips.

4. The wafer testing method as recited in claim 1 , further comprising a problem-eliminating step, after the auto-recovery data generating step and before the second testing step, so as to ensure the first testing unit operating properly.

5. The wafer testing method as recited in claim 4 , wherein, during the second testing step, the first testing unit is used for continuing the testing, based on the auto-recovery data, from a chip being last but incompletely tested.

6. The wafer testing method as recited in claim 1 , further comprising a transfer step, after the auto-recovery data generating step and before the second testing step, so as to transfer the wafer from the first testing unit to a second testing unit.

7. The wafer testing method as recited in claim 6 , during the second testing step, the second testing unit is used for continuing the testing, based on the auto-recovery data, from a chip being last but incompletely tested.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049746/0981 →
CHANGE OF NAME Recorded Jun 24, 2019
From: POWERCHIP SEMICONDUCTOR CORP.
To: POWERCHIP TECHNOLOGY CORPORATION
Reel/Frame 049562/0154 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2004
From: WU, CHIOU-PING; LIN, HSIU-MIN
To: POWERCHIP SEMICONDUCTOR CORP.
Reel/Frame 014904/0278 →