Method of forming a wafer backside interconnecting wire
View Patent ↗A method of forming a wafer backside interconnecting wire includes forming a mask layer on the back surface, the mask layer including at least an opening corresponding to the bonding pad, performing a first etching process from the back surface to remove the wafer unprotected by the mask layer to form a recess, removing the mask layer, and forming an interconnecting wire on the back surface.
1. A method of forming a wafer backside interconnecting wire, the wafer comprising a front surface, a back surface, at least a circuit element positioned on the front surface, and at least a bonding pad positioned on the front surface and electrically connected to the circuit element, the method comprising:
forming a mask layer on the back surface, the mask layer comprising at least an opening corresponding to the bonding pad;
performing a first etching process from the back surface to remove the wafer unprotected by the mask layer to form a recess, the first etching process being isotropic, wherein after the first etching process is performed, the recess has a round shape and the bonding pad is kept unexposed;
removing the mask layer;
performing a second etching process from the back surface to etch the wafer until exposing the bonding pad after removing the mask layer; and
forming an interconnecting wire on the back surface.
2. The method of claim 1 , wherein the wafer further comprises a cap wafer bonded to the front surface of the wafer.
3. The method of claim 2 , wherein the cap wafer is bonded to the front surface with a bonding layer.
4. The method of claim 2 , wherein the cap wafer is bonded to the front surface by an anodic bonding technique.
5. The method of claim 2 , wherein the cap wafer is bonded to the front surface by a plasma enhanced bonding technique.
6. The method of claim 1 , further comprising performing a wafer thinning process from the back surface prior to forming the mask layer on the back surface.
7. The method of claim 6 , wherein the wafer thinning process is implemented by selectively performing one or any combinations of the processes selected from the group consisting of a grinding process, a polishing process, a chemical mechanical polishing process, a wet etching process, and a plasma etching process.
8. The method of claim 6 , wherein the wafer thinning process is a silicon-on-insulator (SOI) wafer thinning process.
9. The method of claim 6 , wherein the thickness of the wafer is less than 100 micrometers subsequent to the wafer thinning process.
10. The method of claim 1 , wherein forming the interconnecting wire comprises the steps of:
forming an insulating layer on the back surface, the insulating layer covering the back surface, the wafer inside the recess, and the bonding layer;
forming a photoresist layer, the photoresist layer having an opening corresponding to the bonding pad;
removing the insulating layer uncovered by the photoresist layer to expose the bonding pad;
removing the photoresist layer; and
forming the interconnecting wire on the back surface.
11. The method of claim 10 , wherein the interconnecting wire is defined by depositing and etching technologies.
12. The method of claim 10 , wherein the interconnecting wire is defined by thin film technologies in combination with a shadow mask.
13. The method of claim 1 , wherein the bonding pad is a metal bonding pad.
14. A method of forming a wafer backside interconnecting wire, the wafer comprising a front surface, a back surface, at least a circuit element positioned on the front surface, and at least a bonding pad positioned on the front surface and electrically connected to the circuit element, the method comprising:
forming a mask layer on the back surface, the mask layer comprising at least an opening corresponding to the bonding pad;
performing a first etching process from the back surface to remove the wafer unprotected by the mask layer to form a recess, the first etching process being anisotropic, wherein subsequent to performing the first etching process, the sidewall of the recess is inclined outward, and the bonding pad is exposed;
removing the mask layer; and
forming an interconnecting wire on the back surface.
15. The method of claim 14 , wherein the wafer further comprises a cap wafer bonded to the front surface of the wafer.
16. The method of claim 15 , wherein the cap wafer is bonded to the front surface with a bonding layer.
17. The method of claim 15 , wherein the cap wafer is bonded to the front surface by an anodic bonding technique.
18. The method of claim 15 , wherein the cap wafer is bonded to the front surface by a plasma enhanced bonding technique.
19. The method of claim 14 , further comprising performing a wafer thinning process from the back surface prior to forming the mask layer on the back surface.
20. The method of claim 19 , wherein the wafer thinning process is implemented by selectively performing one or any combinations of the processes selected from the group consisting of a grinding process, a polishing process, a chemical mechanical polishing process, a wet etching process, and a plasma etching process.