IP Library › Granted Patent US 7,010,046
Granted Patent B2
US 7,010,046 · App. 10/137,015 · Granted Mar 7, 2006

Method and/or architecture for implementing MPEG frame display using four frame stores

Assignee: LSI Logic Corporation
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Quick Facts
Patent No.
US 7,010,046
App. No.
10/137,015
Granted
Mar 7, 2006
Kind
B2
Abstract

An apparatus comprising a decode frame store, a B frame store, a first anchor frame store, and a second anchor frame store. The decode frame store may be configured to decode one or more free frames and generate one or more B video images and one or more anchor video images. The B frame store may be configured to receive the one or more B video images from the decode frame store. The first anchor frame store may be configured to receive the one or more anchor video images from the decode frame store. The second anchor frame store may be configured to receive the one or more anchor video images from the first anchor frame store.

Claims (37)

1. An apparatus comprising:

a decode frame store configured to decode one or more free frames and generate one or more B video images and one or more anchor video images;

a B frame store configured to receive said one or more B video images from said decode frame store;

a first anchor frame store configured to receive said one or more anchor video images from said decode frame store; and

a second anchor frame store configured to receive said one or more anchor video images from said first anchor frame store, wherein said apparatus further comprises one or more post-process decode engines coupled to said decode frame store and configured to generate said one or more B and said one or more anchor video images provide (i) additional graphics, (ii) video scaling, and (iii) post-decode display controller processes.

2. The apparatus according to claim 1 , wherein said decode frame store comprises (i) an unused frame store configured as a free frame pool configured to store said one or more free frames, (ii) a decoding frame store configured to generate said one or more B video images and said one or more anchor video images in response to said one or more free frames, and (iii) a decoded frame store configured as a decoded frame pool configured to store said one or more B video images and said one or more anchor video images.

3. The apparatus according to claim 2 , wherein said unused frame store and said decoded frame store each comprise one or more first-in/first-out (FIFO) memories.

4. The apparatus according to claim 2 , wherein said apparatus further comprises a display frame configured (i) to receive said B video images from said B frame store in a first mode of operation and said anchor video images from said second anchor frame in a second mode of operation and (ii) to display a current video image in response to said B and anchor video images.

5. The apparatus according to claim 4 , wherein said apparatus is configured to provide a delay time that is less than or equal to a single frame time period between decoding said one or more free frames and displaying said current video image.

6. The apparatus according to claim 4 , wherein said display frame is further configured to present a previously displayed video image to said unused frame store.

7. The apparatus according to claim 1 , wherein said first anchor frame store comprises a forward anchor frame store and said second anchor store comprises a backward anchor frame store.

8. The apparatus according to claim 1 , wherein (i) said decode frame store, said B frame store, said first anchor frame store, and said second anchor frame store comprise a four frame decoder, (ii) said B frame store, said first anchor frame store, and said second anchor frame store comprise a three frame decoder with decoding performed in said B frame in response to said one or more free frames, and (iii) said apparatus is configured as said three frame decoder during a first display mode and said four frame decoder during a second display mode.

9. The apparatus according to claim 8 , wherein said apparatus is configured as said four frame decoder exclusively.

10. A method for decoding and displaying video images comprising the steps of:

(A) decoding one or more B video images and one or more anchor video images in response to one or more free frames, wherein said decoding comprises (i) storing said one or more free frames in a first decode frame store configured as a free frame pool, (ii) decoding said one or more free frames in a second decode frame store, and (iii) storing said decoded frames in a third decode frame store configured as a decoded frame pool;

(B) presenting said one or more B video images to a B video image store;

(C) presenting said one or more anchor video images to a first anchor video image store; and

(D) transferring said one or more anchor video images from said first anchor video image store to a second anchor video image store.

11. The method according to claim 10 , wherein said first decode frame store and said third decode frame store each comprise one or more first-in/first-out (FIFO) memories.

12. The method according to claim 10 , wherein sub-step (A-2) further comprises the sub-step of:

decoding said free frames via one or more decode engines coupled to said second decode frame store.

13. The method according to claim 10 , wherein step (A) further comprises the sub-step of:

delaying a display operation following said decoding operation by a period having a duration less than or equal to a single frame time period.

14. The method according to claim 10 , further comprising the steps of:

retrieving one of said decoded frames from said third decode frame store;

when said decoded frame comprises one of said B video images, displaying said video image; and

when said decoded frame comprises one of said anchor video images, displaying said second anchor video image store.

15. The method according to claim 14 , further comprising the steps of:

operating as a three frame decoder during a first display mode; and

operating as a four frame decoder during a second display mode.

16. The method according to claim 15 , further comprising the step of:

operating as said four frame decoder exclusively.

17. An apparatus comprising:

a decode frame store configured to decode one or more free frames and generate one or more B video images and one or more anchor video images;

a B frame store configured to receive said one or more B video images from said decode frame store;

a first anchor frame store configured to receive said one or more anchor video images from said decode frame store; and

a second anchor frame store configured to receive said one or more anchor video images from said first anchor frame store, wherein (i) said decode frame store, said B frame store, said first anchor frame store, and said second anchor frame store comprise a four frame decoder, (ii) said B frame store, said first anchor frame store, and said second anchor frame store comprise a three frame decoder with decoding performed in said B frame in response to said one or more free frames, and (iii) said apparatus is configured as said three frame decoder during a first display mode and said four frame decoder during a second display mode.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2002
From: TREVERS, GARETH D.; GRANDBOIS, BRETT J.
To: LSI LOGIC CORPORATION
Reel/Frame 012863/0454 →
Continuity (1)
Related Publication 20030206228A1 · Nov 6, 2003