Apparatus and method for dynamically enabling and disabling interrupt coalescing in data processing system
An apparatus and method for dynamically enabling and disabling interrupt coalescing in a data processing system. The present invention involves consistently monitoring IO load on an IOP of an IO adapter. The firmware on the IO adapter may have a global variable that stores counters for PCI function registers. Each counter tracks the number of outstanding IOs of a corresponding PCI function register. The counter is incremented whenever a new IO is received and is decremented upon posting the completed message back to the OS. A timer interrupt is generated periodically so that an ISR may be periodically performed. In the ISR, the maximum value stored of each counter seen since last timer interrupt is analyzed. When the maximum value stored is greater than a predetermined threshold value, the interrupt coalescing is enabled.
1. A method for dynamically enabling and disabling interrupt coalescing in a data processing system, comprising:
providing a counter suitable for tracking input/output load of an input/output processor, wherein the counter is incremented when a new input/output request is received by the input/output processor, and is decremented when the input/output processor posts a completed message back to a host processor;
generating a timer interrupt periodically so that an interrupt service routine is periodically performed;
comparing a current value of the counter with a store of a highest value of the counter seen since last timer interrupt when the input/output processor iterates a polling loop, wherein the current value becomes a maximum value stored when the current value is greater, and the highest value is the maximum value stored when the current value is not greater;
comparing the maximum value stored with a first predetermined threshold value in the interrupt service routine; and
enabling the interrupt coalescing when the maximum value stored is greater than the first predetermined threshold value.
2. The method of claim 1 , further comprising disabling the interrupt coalescing when the maximum value stored is not greater than the first predetermined threshold value.
3. The method of claim 1 , further comprising disabling the interrupt coalescing when the maximum value stored is less than a second predetermined threshold value, wherein the second predetermined threshold value is a value less than the first predetermined threshold value.
4. The method of claim 3 , further comprising maintaining a status quo of an interrupt coalescing state when the maximum value stored is neither greater than the first predetermined threshold value nor less than the second predetermined threshold value.
5. An apparatus for dynamically enabling and disabling interrupt coalescing in a data processing system, comprising:
means for providing a counter suitable for tracking input/output load of an input/output processor, wherein the counter is incremented when a new input/output request is received by the input/output processor, and is decremented when the input/output processor posts a completed message back to a host processor;
means for generating a timer interrupt periodically so that an interrupt service routine is periodically performed;
means for comparing a current value of the counter with a store of a highest value of the counter seen since last timer interrupt when the input/output processor iterates a polling loop, wherein the current value becomes a maximum value stored when the current value is greater, and the highest value is the maximum value stored when the current value is not greater;
means for comparing the maximum value stored with a first predetermined threshold value in the interrupt service routine; and
means for enabling the interrupt coalescing when the maximum value stored is greater than the first predetermined threshold value.
6. The apparatus of claim 5 , further comprising means for disabling the interrupt coalescing when the maximum value stored is not greater than the first predetermined threshold value.
7. The apparatus of claim 5 , further comprising means for disabling the interrupt coalescing when the maximum value stored is less than a second predetermined threshold value, wherein the second predetermined threshold value is a value less than the first predetermined threshold value.
8. The apparatus of claim 7 , further comprising means for maintaining a status quo of an interrupt coalescing state when the maximum value stored is neither greater than the first predetermined threshold value nor less than the second predetermined threshold value.
9. An apparatus for dynamically enabling and disabling interrupt coalescing in a data processing system, comprising:
a host processor including a PCI function register;
a counter suitable for tracking a number of outstanding input/output load of the PCI function register, wherein the counter is incremented when a new input/output request is received, and is decremented upon posting a completed message back to the host processor;
an IO adapter coupled to the host processor, wherein the IO adapter includes an input/output processor suitable for enabling and disabling interrupt coalescing and suitable for iterating a polling loop, and wherein firmware on the IO adapter has a global variable that stores the counter;
means for generating a timer interrupt periodically so that an interrupt service routine is periodically performed;
means for comparing a current value of the counter with a store of a highest value of the counter seen since last timer interrupt when the input/output processor iterates the polling loop, wherein the current value becomes a maximum value stored when the current value is greater, and the highest value is the maximum value stored when the current value is not greater; and
means for comparing the maximum value stored with a predetermined threshold value in the interrupt service routine.
10. The apparatus of claim 9 , wherein the IO adapter is a MPT based controller.
11. The apparatus of claim 10 , wherein the MPT based controller is of a single-channel design.
12. The apparatus of claim 11 , wherein the MPT based controller is a SCSI controller.
13. The apparatus of claim 10 , wherein the MPT based controller is of a multi-channel design.
14. The apparatus of claim 13 , wherein the MPT based controller is a SCSI controller.
15. The apparatus of claim 10 , wherein the input/output processor is based on an ARM microprocessor core.