IP Library Granted Patent US 7,059,859
Granted Patent B2
US 7,059,859 · App. 11/038,502 · Granted Jun 13, 2006

Manufacturing method of semiconductor device

Assignee: Sanyo Electric Co., Ltd.
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Quick Facts
Patent No.
US 7,059,859
App. No.
11/038,502
Granted
Jun 13, 2006
Kind
B2
Abstract

In a semiconductor device having a MOS transistor and a diffused resistor layer, a leakage current of a diffused resistor layer is suppressed. A film of gate electrode material is formed over the entire surface of an N-type well, a photoresist layer is formed to mask a region to form a gate electrode and portions of the diffused resistor layer and the gate electrode and a damage prevention films are formed by anisotropically etching the film of gate electrode material. After forming a CVD insulation film over the entire surface of the N-type well, sidewall spacers are formed on sidewalls of the gate electrode and the damage prevention films by anisotropically etching the CVD insulation film. A source layer and a drain layer of the MOS transistor and contact regions to the diff-used resistor layer are formed by doping portions of the N-type well and the diffused resistor layer with high concentration P-type impurities using the gate electrode, the damage prevention film and the sidewall spacers as a mask.

Claims (26)

1. A method of manufacturing a semiconductor device comprising a MOS transistor and a diffused resistor layer that are formed on a semiconductor substrate, the method comprising:

forming an isolation layer on the semiconductor substrate;

forming a gate insulation film on the semiconductor substrate;

forming the diffused resistor layer by doping with a low concentration of impurities a portion of the semiconductor substrate defined by the device isolation layer;

forming a film of a gate electrode material on the device isolation layer and the gate insulation film;

forming a mask on the film of the gate electrode material to cover portions of the film of the gate electrode material that correspond to a gate electrode of the MOS transistor and an area of the diffused resistor layer;

etching the film of the gate electrode material using the mask so that the gate electrode and a damage prevention film are formed;

forming a spacer insulation film over a surface of the semiconductor substrate on which the gate electrode and the damage prevention film are formed; and

etching the spacer insulation film so that a sidewall spacer is formed on a sidewall of the gate electrode and another sidewall spacer is formed on a sidewall of the damage prevention film.

2. The method of claim 1 , further comprising doping portions of the semiconductor substrate with a high concentration of impurities using the gate electrode, the damage prevention film and the sidewall spacers as a mask so that a source layer and a drain layer of the MOS transistor are formed.

3. The method of claim 1 , wherein the forming of the spacer insulation film comprises a chemical vapor deposition.

4. The method of claim 1 , further comprising forming a bipolar transistor on the semiconductor substrate.

5. A method of manufacturing a semiconductor device comprising a MOS transistor and a diffused resistor layer of a first conductivity type that are formed on a semiconductor substrate of the first conductivity type, the method comprising:

forming a well of a second conductivity type on the semiconductor substrate;

forming a device isolation layer on the well;

forming a gate insulation film on the well;

forming a photoresist layer having an opening above a first region of the well defined by the device isolation layer;

doping the first region of the well with a low concentration of impurities of the first conductivity type through the opening of the photoresist layer so that the diffused resistor layer of the first conductivity type is formed;

forming a film of a gate electrode material on the device isolation layer and the gate insulation film;

forming a mask on the film of the gate electrode material to cover portions of the film of the gate electrode material that correspond to a gate electrode of the MOS transistor and an area of the diffused resistor layer;

etching the film of gate the electrode material using the mask so that the gate electrode and a damage prevention film are formed;

forming a spacer insulation film over a surface of the semiconductor substrate on which the gate electrode and the damage prevention film are formed;

etching the spacer insulation film so that a sidewall spacer is formed on a sidewall of the gate electrode and another sidewall spacer is formed on a sidewall of the damage prevention film; and

doping second regions of the well and portions of the diffused resistor layer with a high concentration of impurities of the first conductivity type using the gate electrode, the damage prevention film and the sidewall spacers as a mask so that a source layer and a drain layer of the MOS transistor and contact regions to the diffused resistor layer are formed.

6. The method of claim 5 , wherein the forming of the spacer insulation film comprises a chemical vapor deposition.

7. The method of claim 5 , further comprising forming a bipolar transistor on the semiconductor substrate.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 26, 2005
From: MIYAWAKI, YOSHIHIKO
To: SANYO ELECTRIC CO., LTD.
Reel/Frame 016501/0315 →
Priority Claims (1)
JP 2004-013427 · Jan 21, 2004 · national
Continuity (1)
Related Publication 20050181589A1 · Aug 18, 2005