Method and apparatus for secure scan testing
A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan chain again prior to exiting test mode and resuming normal operation. Clearing or otherwise modifying data stored in the scan-observable portions of a processor when transitioning to and/or from a test mode will prevent unauthorized personnel from simply shifting secure data out of the scan chain, and from pre-loading data into the scan chain prior to normal operation in an attempt to set sensitive state information.
1. A method comprising:
receiving an asserted reset signal to place a scan chain of a data processor in a reset state;
receiving an asserted scan test signal, subsequent to the asserted reset signal being negated, to enable entering a scan test mode to read information that is present in the scan chain prior to receiving the asserted scan test signal, wherein data in the scan chain can be shifted during the scan test mode;
modifying data in the scan chain in response to receiving the asserted scan test signal and prior to shifting data in the scan chain; and
enabling shifting of data in the scan chain during scan test mode in response to receiving the asserted scan test signal and after modifying the data in the scan chain.
2. The method as in claim 1 , wherein:
modifying the data comprises modifying a portion of the data stored in the scan chain in response to receiving the asserted scan test signal.
3. The method as in claim 2 , wherein the portion of the data stored in the scan chain is associated with a secure portion of the data processor.
4. The method as in claim 1 , wherein, prior to enabling, data in the scan chain is prevented from being shifted between a plurality of scan latches comprising the scan chain.
5. The method as in claim 1 , wherein, prior to enabling, data in the scan chain is prevented from being shifted out of the data processor.
6. The method as in claim 1 , wherein enabling further comprises enabling shifting of data in the scan chain a predetermined number of clock cycles after receiving the asserted scan test signal.
7. The method as in claim 1 further comprising:
initiating an event in response to receiving the asserted scan test signal; and
wherein enabling shifting is performed in response to receiving an event trigger signal generated in response to execution of the event.
8. The method as in claim 7 , wherein initiating the event comprises the event being a modify memory operation.
9. The method as in claim 8 , wherein the event trigger signal is generated upon completion of the modify memory operation.
10. The method as in claim 7 , wherein the event trigger signal is generated upon completion of the event.
11. The method of claim 1 wherein modifying the data occurs after receiving the data in response to a clock cycle, and enabling includes enabling the shifting of data after the clock cycle.
12. The method as in claim 1 further comprising:
receiving a negated scan test signal to enable operating the data processor in a normal mode of operation after receiving the reset signal and before receiving the asserted scan test signal.
13. The method as in claim 1 further comprising:
receiving a negated scan test signal to enable operating the data processor in a normal mode of operation after enabling shifting of the data; and
modifying data in the scan chain in response to receiving the negated scan test signal.
14. The method as in claim 13 , wherein modifying data in the scan chain in response to receiving the negated scan test signal comprises modifying data in a same portion of the scan chain as is modified when modifying data in the scan chain in response to receiving the asserted scan test signal.
15. The method as in claim 13 , wherein modifying data in the scan chain in response to receiving the negated scan test signal comprises modifying data in a different portion of the scan chain as is modified when modifying data in the scan chain in response to receiving the asserted scan test signal.
16. The method as in claim 13 , further comprising:
entering normal mode of operation at the data processor, subsequent to modifying data in the scan chain, in response to receiving the negated scan test signal.
17. A system comprising:
a means for receiving an asserted reset signal at a data processor to place a scan chain of the data processor in a reset state;
a means for receiving an asserted scan test signal, at the data processor subsequent to the reset signal being negated, to enable entering a scan test mode to read information that is stored in the scan chain prior to receiving the asserted scan test signal, wherein data in the scan chain can be shifted during the scan test mode;
a means for modifying data in the scan chain in response to receiving the asserted scan test signal and prior to shifting data in the scan chain; and
a means for enabling shifting of data in the scan chain during scan test mode in response to receiving the asserted scan test signal after modifying the data in the scan chain.
18. The system as in claim 17 , wherein the means for modifying data in the scan chain comprises means for modifying a portion of the data stored in the scan chain in response to receiving the asserted scan test signal.
19. The system as in claim 18 , wherein the portion of the data stored in the scan chain is associated with a secure portion of the data processor.