Trench metal-insulator-metal (MIM) capacitors integrated with middle-of-line metal contacts, and method of fabricating same

1. A semiconductor device comprising:

at least one trench capacitor located in a trench in a substrate, said at least one trench capacitor comprising inner and outer metallic electrode layers with a dielectric layer therebetween;

at least one field effect transistor (FET) located on said substrate, said at least one FET comprising a source region, a drain region, a channel region, and at least one metal contact connected with the source or drain region, wherein the inner metallic electrode layer of the trench capacitor and the metal contact of the field effect transistor comprise essentially the same metallic material; and

at least one metallic strap located beneath a top surface of said substrate and directly contacting both said inner metallic electrode layer and one of said source region and said drain region, wherein a top surface of said inner metallic layer is located above said at least one metallic strap.

2. The semiconductor device of claim 1 , wherein the inner metallic electrode layer of the wench capacitor and the metal contact of the field effect transistor comprise at least one metal or metal alloy selected from the group consisting of tungsten, copper, silver, and aluminum.

3. The semiconductor device of claim 1 , wherein the metallic strap comprises a metal silicide or a silicidated metal nitride.

4. The semiconductor device of claim 1 , wherein the outer metallic electrode layer of the trench capacitor comprises a metal silicide or a composite of a metal silicide and a metal nitride.

5. The semiconductor device of claim 1 , wherein the dielectric layer of the trench capacitor comprises a high dielectric constant material having a dielectric constant of greater than 4.

6. The semiconductor device of claim 1 , wherein the substrate comprises a semiconductor-on-insulator structure.

7. The semiconductor device of claim 1 , wherein the substrate comprises a bulk semiconductor structure.

8. The semiconductor device of claim 1 , wherein the metal contact of the FET is connected to a bitline.

9. The semiconductor device of claim 8 , wherein the inner metallic electrode layer of the trench capacitor is electrically isolated from said bitline.

10. A method for forming a semiconductor device comprising:

forming at least one field effect transistor (FET) on a substrate, wherein said at least one FET comprises a source region, a drain region, and a channel region; forming at least two trenches in said substrate, the first of which stops at and exposes the source or drain region of the FET, and the second of which is adjacent to the FET and has a depth larger than that of the first trench; forming an outer metallic electrode layer and a dielectric layer for a trench capacitor in the second trench; and

filling both the first and second trenches with a metallic material to concurrently form an inner metallic electrode layer for the trench capacitor and a metal contact for the FET.

11. The method of claim 10 , wherein the FET is covered by at least one middle-of-line insulator layer and at least one dielectric capping layer before formation of the trenches.

12. The method of claim 10 , wherein the inner metallic electrode layer of the trench capacitor and the metal contact of the field effect transistor comprise at least one metal or metal alloy selected from the group consisting of tungsten, copper, silver, and aluminum.

13. The method of claim 10 , wherein during formation of the outer metallic electrode layer of the trench capacitor, a metallic strap is formed on a sidewall of the second trench, wherein said metallic strap is electrically connected to the source or drain region of the FET, and wherein the subsequently formed inner metallic electrode layer of the trench capacitor is electrically connected to the source or drain region of the FET by said metallic strap.

14. The method of claim 13 , wherein the metallic strap comprises a metal silicide or a composite of metal silicide and metal nitride.

15. The method of claim 10 , wherein the outer metallic electrode layer of the trench capacitor comprises a metal silicide or a silicidated metal nitride.

16. The method of claim 10 , wherein the substrate comprises a semiconductor-on-insulator structure.

17. The method of claim 10 , wherein the substrate comprises a bulk semiconductor structure.

18. The method of claim 10 , wherein the metal contact of the FET is connected to a bitline, and wherein the inner metallic electrode layer of the trench capacitor is electrically isolated from said bitline.

19. A semiconductor device comprising:

at least one trench capacitor that is located in a substrate, said at least one trench capacitor comprising inner and outer metallic electrode layers with a dielectric layer therebetween, wherein a top surface of said inner metallic electrode layer is located above a top surface of said substrate; and

at least one metal contact connected with at least one logic circuitry component selected from the group consisting of transistors, resistors, diodes, planar capacitor, arid varactors, wherein said at least one logic circuitry component is covered by at least one insulator layer, wherein said at least one metal contact is located in a trench in said at least one insulator layer, and wherein the inner metallic electrode layer of the trench capacitor and the at least one metal contact comprise essentially the same metallic material.