Semiconductor device with bonding pad support structure
A semiconductor device having bonding pads on a semiconductor substrate includes: an upper copper layer that is formed on the lower surface of the bonding pads with a barrier metal interposed and that has a copper area ratio that is greater than layers in which circuit interconnects are formed; and a lower copper layer that is electrically insulated from the upper copper layer and that is formed closer to the semiconductor substrate than the upper copper layer.
1. A semiconductor device, comprising:
a bonding pad on a semiconductor substrate;
an upper copper layer on a lower surface of said bonding pad with a barrier metal interposed; and
a lower copper layer closer to said semiconductor substrate than said upper copper layer;
wherein a copper area ratio of said lower copper layer under said bonding pad is lower than that of said upper copper layer, and
wherein said lower copper layer is not electrically connected to said upper copper layer under said bonding pad.
2. A semiconductor device according to claim 1 , wherein the copper area ratio of said upper copper layer is greater than that of other copper layers that are formed as circuit interconnects on said semiconductor substrate.
3. A semiconductor device according to claim 1 , wherein the copper area ratio of said upper copper layer is at least 70%.
4. A semiconductor device according to claim 1 , wherein the planar dimensions of said bonding pad and said upper copper layer are substantially equal.
5. A semiconductor device according to claim 1 , wherein said upper copper layer is constituted by a plurality of copper layers.
6. A semiconductor device according to claim 5 , wherein the copper area ratios of each copper layer of said upper copper layer are substantially the same.
7. A semiconductor device according to claim 5 , further comprising:
interlevel dielectric films that are provided between each of the copper layers of said upper copper layer; and
via-plugs composed of copper that are embedded in said interlevel dielectric films;
wherein each of the copper layers of said upper copper layer are connected by way of said via-plugs.
8. A semiconductor device according to claim 7 , wherein the copper layer pattern of the copper layer that is positioned uppermost in said upper copper layer and said via-plugs that are connected to the copper layer pattern are embedded in a dielectric film that is composed of a first material.
9. A semiconductor device according to claim 1 , wherein the copper area ratio of said lower copper layer is at least 15% and not greater than 95%.
10. A semiconductor device according to claim 8 , wherein said lower copper layer is constituted by a plurality of copper layers.
11. A semiconductor device according to claim 10 , wherein each of the copper layers of said lower copper layer are constituted by a copper pattern that is embedded in a dielectric film that is composed of a second material having a lower relative dielectric constant than said first material.
12. A semiconductor device comprising:
a bonding region in which a bonding pad is formed;
an internal circuit region provided inside of said bonding region, said internal circuit region having a multilevel wiring structure that includes a plurality of copper interconnect layers at a first level and a plurality of copper interconnect layers at second level; and
an upper copper layer formed in said bonding region above said internal circuit region and under said bonding pad in electrical contact therewith, said upper copper layer being electrically isolated from said internal circuit region.
13. The device as claimed in claim 12 , wherein one of said copper interconnect layers at said second level is further elongated from said internal circuit region to said bonding region under said upper copper layer in electrical isolation from said upper copper layer and from one of said copper interconnect layers at said first level.
14. The device as claimed in claim 12 , wherein said upper copper layer includes first and second copper layers and a via-plug sandwiched therebetween.
15. The device as claimed in claim 14 , further comprising a plurality of copper interconnect layers at a third level and a plurality of copper interconnect layers at a fourth level, said first copper layer being formed at said third level and said second copper layer being formed at said fourth level.
16. The device as claimed in claim 15 , wherein said bonding pad is in electrical contact with said second copper layer, and one of said copper interconnect layers at said fourth level has an electrical contact with said second copper layer.
17. The device as claimed in claim 13 , wherein said upper copper layer includes first and second copper layers and a via-plug sandwiched therebetween, and said bonding pad is in electrical contact with said second copper layer.
18. The device as claimed in claim 17 , further comprising a plurality of copper interconnect layers at a third level and a plurality of copper interconnect layers at a fourth level, said first copper layer being formed at said third level and said second copper layer being formed at said fourth level.
19. The device as claimed in claim 18 , wherein said bonding pad is in electrical contact with said second copper layer via a barrier metal layer and one of said copper interconnect layers at said fourth level has an electrical contact with said second copper layer.
20. The semiconductor device according to claim 1 , wherein the upper copper layer is separated from the lowest surface of said bonding pad only by the barrier metal.
21. The device as claimed in claim 12 , wherein said upper copper layer is separated from the lowest surface of said bonding pad only by a layer of a barrier metal.