IP Library › Granted Patent US 7,439,578
Granted Patent B2
US 7,439,578 · App. 11/617,517 · Granted Oct 21, 2008

Semiconductor device

Assignee: Sanyo Electric Co., Ltd.
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Quick Facts
Patent No.
US 7,439,578
App. No.
11/617,517
Granted
Oct 21, 2008
Kind
B2
Abstract

A semiconductor device includes a trench formed in a surface of a semiconductor substrate. A conductor is embedded in the trench. A conductive layer is arranged adjacent to the trench on the surface of the semiconductor substrate. Semiconductor elements, which include sources provided by one of the conductor and the conductive layer and drains provided by the other one of the conductor and the conductive layer, are formed in a semiconductor element formation region. A planar wiring layer is embedded in the semiconductor substrate under the entire semiconductor element formation region and connected to the conductor.

Claims (39)

1. A semiconductor device comprising:

a semiconductor substrate having a surface;

a trench formed in the surface of the semiconductor substrate;

a conductor embedded in the trench;

a conductive layer arranged adjacent to the trench on the surface of the semiconductor substrate;

a plurality of semiconductor elements including sources provided by one of the conductor and the conductive layer and drains provided by the other one of the conductor and the conductive layer;

a semiconductor element formation region for forming the plurality of semiconductor elements therein; and

a planar wiring layer embedded in the semiconductor substrate under the entire semiconductor element formation region and connected to the conductor.

2. The semiconductor device according to claim 1 , further comprising:

a plurality of metal wires arranged on the semiconductor substrate and including a first metal wire connected to the conductor and a second metal wire connected to the conductive layer, wherein the first metal wire has a wire width that is narrower than that of the second metal wire.

3. The semiconductor device according to claim 1 , wherein:

the plurality of semiconductor elements are arranged in a first direction;

the trench extends in a second direction; and

the planar wiring layer has a first dimension measured in the first direction and a second dimension measured in the second direction, and a ratio of the second dimension to the first dimension is one or less.

4. The semiconductor device according to claim 3 , wherein the planar wiring layer is rectangular.

5. The semiconductor device according to claim 1 , wherein the conductor has a lower end that terminates in the planar wiring layer.

6. The semiconductor device according to claim 1 , wherein the conductor is one of more than two conductors each having a lower end, and the planar wiring layer is a single layer that electrically and mutually connects the lower ends of the more than two conductors.

7. The semiconductor device according to claim 6 , wherein the planar wiring layer is located at a constant depth as measured in a depth direction from the surface of the semiconductor substrate.

8. The semiconductor device according to claim 7 , wherein the lower ends of the more than two conductors do not extend through the planar wiring layer.

9. A semiconductor device comprising:

a semiconductor substrate having a surface;

a trench formed in the surface of the semiconductor substrate;

a gate electrode embedded in the trench;

a conductor embedded inward from the gate electrode;

a conductive layer arranged adjacent to the trench on the surface of the semiconductor substrate;

a plurality of semiconductor elements including sources provided by one of the conductor and the conductive layer and drains provided by the other one of the conductor and the conductive layer;

a semiconductor element formation region for forming the plurality of semiconductor elements therein; and

a planar wiring layer embedded in the semiconductor substrate under the entire semiconductor element formation region and connected to the conductor.

10. The semiconductor device according to claim 9 , further comprising:

a plurality of metal wires arranged on the semiconductor substrate and including a first metal wire connected to the conductor and a second metal wire connected to the conductive layer, wherein the first metal wire has a wire width that is narrower than that of the second metal wire.

11. The semiconductor device according to claim 9 , wherein:

the plurality of semiconductor elements are arranged in a first direction;

the trench extends in a second direction; and

the planar wiring layer has a first dimension measured in the first direction and a second dimension measured in the second direction, and a ratio of the second dimension to the first dimension is one or less.

12. The semiconductor device according to claim 11 , wherein the planar wiring layer is rectangular.

13. The semiconductor device according to claim 9 , wherein the conductor has a lower end that terminates in the planar wiring layer.

14. The semiconductor device according to claim 9 , wherein the conductor is one of more than two conductors each having a lower end, and the planar wiring layer is a single layer that electrically and mutually connects the lower ends of the more than two conductors.

15. The semiconductor device according to claim 14 , wherein the planar wiring layer is located at a constant depth as measured in a depth direction from the surface of the semiconductor substrate.

16. The semiconductor device according to claim 15 , wherein the lower ends of the more than two conductors do not extend through the planar wiring layer.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 2, 2007
From: TAKEDA, YASUHIRO; MORIGAMI, MITSUAKI; SHIMADA, SATORU; YOSHITAKE, KAZUHIRO; KIKUCHI, SHUICHI; OTAKE, SEIJI; OHKODA, TOSHIYUKI
To: SANYO ELECTRIC CO., LTD.
Reel/Frame 019099/0012 →
Priority Claims (2)
JP 2005-376788 · Dec 28, 2005 · national
JP 2006-083269 · Mar 24, 2006 · national
Continuity (1)
Related Publication 20070166925A1 · Jul 19, 2007