Memory cell and method for forming the same
A semiconductor memory cell structure having 4F 2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a capacitor is formed on the semiconductor post. A vertical access transistor having a gate structure formed on the semiconductor post is configured to electrically couple the respective memory cell capacitor to the active region when accessed.
1. A memory cell formed on a surface of a substrate, comprising:
a memory cell capacitor; and
a vertical transistor comprising:
an active region formed in the substrate;
an epitaxial post extending from the surface of the substrate over the active region, the epitaxial post having a lightly doped conductive region formed therein to electrically couple the memory cell capacitor to the epitaxial post of the vertical transistor, the memory cell capacitor formed over the epitaxial post; and
a gate formed at least partially around a perimeter of the epitaxial post.
2. The memory cell of claim 1 wherein the memory cell capacitor comprises a container-shaped capacitor structure.
3. The memory cell of claim 1 wherein the memory cell capacitor comprises a stacked capacitor structure.
4. The memory cell of claim 1 wherein the memory cell capacitor comprises a finned capacitor structure.
5. The memory cell of claim 1 wherein the epitaxial post comprises a generally quadrilateral cross-sectional area.
6. The memory cell of claim 1 wherein the epitaxial post comprises a generally circular cross-sectional area.
7. The memory cell of claim 1 wherein the epitaxial post comprises a generally polygonal cross-sectional area.
8. A memory cell formed on a surface of a substrate, comprising:
an active region formed in the substrate and having a highly doped region to promote conductivity to a digit line contact;
a vertical transistor at least partially formed in a semiconductor post, the semiconductor post formed on the surface of the substrate and extending therefrom, the vertical transistor further having a gate formed at least partially around a perimeter of the semiconductor post; and
a memory cell capacitor electrically coupled to the semiconductor post of the vertical transistor.
9. The memory cell of claim 8 wherein the memory cell shares at least one digit contact with an adjacent memory cell, and wherein the digit contact is offset in relation to the semiconductor posts of the memory cell and the adjacent memory cell.
10. The memory cell of claim 8 wherein the memory cell capacitor comprises a container-shaped capacitor structure.
11. The memory cell of claim 8 wherein the memory cell capacitor comprises a stacked capacitor structure.
12. The memory cell of claim 8 wherein the memory cell capacitor comprises a finned capacitor structure.
13. The memory cell of claim 8 wherein the epitaxial post comprises a generally quadrilateral cross-sectional area.
14. The memory cell of claim 8 wherein the epitaxial post comprises a generally circular cross-sectional area.
15. The memory cell of claim 8 wherein the epitaxial post comprises a generally polygonal cross-sectional area.
16. A plurality of memory cells formed on a surface of a substrate, comprising:
an active region formed in the substrate;
a plurality of semiconductor posts formed on the surface of the substrate over the active region;
a plurality of memory cell capacitors each formed over a respective one of the plurality of semiconductor posts; and
a plurality of gate structures each formed adjacent a respective one of the plurality of semiconductor posts to provide a respective vertical transistor configured to electrically couple a respective one of the memory cell capacitors to the active region; and
a digit contact electrically coupled to the active region, the digit contact disposed between first and second adjacent semiconductor posts, the digit contact having a portion extending into a region between the first and second adjacent semiconductor posts.
17. The plurality of memory cells of claim 16 , further comprising an isolation region formed adjacent the active region.
18. The plurality of memory cells of claim 16 wherein the digit contact comprises a digit contact offset in relation to the first and second adjacent semiconductor posts.
19. The plurality of memory cells of claim 16 , further comprising a digit line coupled to the digit contact.
20. The plurality of memory cell of claim 16 wherein the active region comprises a highly doped region to promote conductivity to the digit contact.
21. The plurality of memory cells of claim 16 , further comprising a plurality of digit lines each formed in the substrate and electrically coupled to at least one of the semiconductor posts.
22. A plurality of memory cells formed on a surface of a substrate, comprising:
an active region formed in the substrate;
a plurality of semiconductor posts formed on the surface of the substrate over the active region;
a plurality of memory cell capacitors each formed over a respective one of the plurality of semiconductor posts; and
a plurality of gate structures each formed adjacent a respective one of the plurality of semiconductor posts to provide a respective vertical transistor configured to electrically couple a respective one of the memory cell capacitors to the active region; and
a digit contact electrically coupled to the active region, the digit contact disposed between first and second adjacent semiconductor posts, the digit contact offset in relation to the first and second adjacent semiconductor posts.