Double gate isolation
View Patent ↗A double-gated fin-type field effect transistor (FinFET) structure has electrically isolated gates. In a method for manufacturing the FinFET structure, a fin, having a gate dielectric on each sidewall corresponding to the central channel region, is formed over a buried oxide (BOX) layer on a substrate. Independent first and second gate conductors on either sidewall of the fin are formed and include symmetric multiple layers of conductive material. An insulator is formed above the fin by either oxidizing conductive material deposited on the fin or by removing conductive material deposited on the fin and filling in the resulting space with an insulating material. An insulating layer is deposited over the gate conductors and the insulator. A first gate contact opening is etched in the insulating layer above the first gate. A second gate contact opening is etched in the BOX layer below the second gate.
1. A method of forming gates on a fin of a fin-type field effect transistor (FinFET), said method comprising:
forming a first conductive layer on portions of a first sidewall and a second sidewall of said fin;
forming a second conductive layer over said fin and said first conductive layer;
depositing a third conductive layer over said second conductive layer;
planarizing said third conductive layer to expose a portion of said second conductive layer over said fin; and
changing said exposed portion of said second conductive layer into an insulator.
2. The method of claim 1 , wherein forming a second conductive layer over said fin and said first conductive layer comprises:
further forming said first conductive layer over said fin; and
implanting an outer surface of said first conductive layer with an impurity in sufficient concentrations to enhance the oxidation rate of said outer surface and thereby create said second conductive layer.
3. The method of claim 1 , wherein said process of changing said exposed portion of said second conductive layer into an insulator comprises oxidizing said exposed portion of said second conductive layer.
4. The method of claim 1 , wherein said process of changing said exposed portion of said second conductive layer into an insulator comprises selectively removing said exposed portion of said second conductive layer and filling in said removed portions of said second conductive layer with an insulator.
5. The method of claim 1 , further comprising after forming said first conductive layer and before forming said second conductive layer, etching a gate contact opening in an insulating layer on which said fin is positioned.
6. A method of forming gates on a fin of a fin-type field effect transistor (FinFET), said method comprising:
forming a first conductive layer on portions of a first sidewall and a second sidewall of said fin;
etching a gate contact opening in an insulating layer on which said fin is positioned;
forming a second conductive layer over said fin and said first conductive layer;
depositing a third conductive layer over said second conductive layer;
planarizing said third conductive layer to expose a portion of said second conductive layer over said fin; and
changing said exposed portion of said second conductive layer into an insulator.
7. The method of claim 6 , wherein forming a second conductive layer comprises:
further forming said first conductive layer over said fin; and
implanting an outer surface of said first conductive layer with an impurity in sufficient concentrations to enhance the oxidation rate of said outer surface and thereby create said second conductive layer.
8. The method of claim 6 , wherein said process of changing said exposed portion of said second conductive layer into an insulator comprises oxidizing said exposed portion of said second conductive layer.
9. The method of claim 6 , wherein said method process of changing said exposed portion of said second conductive layer into an insulator comprises selectively removing said exposed portion of said second conductive layer and filling in said removed portions of said second conductive layer with an insulator.