NAND flash memory device and method of forming a well of a NAND flash memory device
Disclosed herein are a NAND flash memory device and a method of forming a well of the NAND flash memory device. Triple wells of a NAND flash memory device are formed within a cell region in plural. A cell block including flash memory cells is formed on the triple wells. Accordingly, during an erase operation of a flash memory device, a stress time for non-selected blocks can be reduced and erase disturbance can be also prevented, through the plurality of the wells. Further, capacitance between the triple P wells and the triple N well is reduced since triple P wells are divided. Therefore, well bias charging and discharging time can be reduced and an overall erase time budget can be thus reduced.
1. A NAND flash memory device comprising:
a semiconductor substrate in which a memory cell region and a peripheral region are defined;
triple N well regions formed in the memory cell region of the semiconductor substrate to electrically protect a plurality of memory cells;
well regions formed in the peripheral region of the semiconductor substrate;
P well regions individually formed in each N well region;
a plurality of cell blocks formed on each triple P well region, wherein each of the cell blocks includes first memory cell strings sharing even bit lines and second memory cell strings sharing odd bit lines;
a plurality of transistors formed on the well regions;
a first page buffer unit coupled to the first memory cell strings formed over different triple N well regions through the even bit lines; and
a second page buffer unit coupled to the second memory cell strings formed over different triple N well regions through the odd bit lines.
2. A NAND flash memory device comprising:
two or more triple N well regions formed in a semiconductor substrate to electrically protect a plurality of memory cells;
P well regions individually formed in each triple N well region; and
a plurality of cell blocks formed on each P well region and including first memory cell strings sharing even bit lines and second memory cell strings sharing odd bit lines;
a first page buffer unit coupled to the first memory cell strings formed over different triple N well regions through the even bit lines; and
a second page buffer unit coupled to the second memory cell strings formed over different triple N well regions through the odd bit lines.
3. The NAND flash memory device of claim 2 , wherein the number of triple N well regions is a multiple of 2 to 3.
4. The NAND flash memory device of claim 2 , further comprising:
well regions for peripheral devices formed in a peripheral region of the semiconductor substrate; and
a plurality of transistors formed on the well regions.
5. A NAND flash memory device comprising:
a triple N well region formed in a memory cell region of a semiconductor substrate;
two or more triple P well regions formed in the triple N well region;
a plurality of cell blocks formed on each P well region and including first memory cell strings sharing even bit lines and second memory cell strings sharing odd bit lines;
a first page buffer unit coupled to the first memory cell strings formed over different triple N well regions through the even bit lines; and
a second page buffer unit coupled to the second memory cell strings formed over different triple N well regions through the odd bit lines.
6. The NAND flash memory device of claim 5 , wherein the number of triple P well regions is a ultiple of 2 or 3.
7. The NAND flash memory device of claim 5 , further comprising:
well regions for peripheral devices formed in a peripheral region of the semiconductor substrate; and
a plurality of transistors formed on the well regions.
8. A NAND flash memory device comprising:
a semiconductor substrate in which a memory cell region and a peripheral region are defined;
a triple N well region formed in the memory cell region of the semiconductor substrate;
well regions formed in the peripheral region of the semiconductor substrate;
two or more triple P well regions formed in the triple N well region,;
a plurality of cell blocks formed on each triple P well region, wherein each of the cell blocks includes first memory cell strings sharing even bit lines and second memory cell strings sharing odd bit lines;
a plurality of transistors formed on the well regions;
a first page buffer unit coupled to the first memory cell strings formed over different triple N well regions through the even bit lines; and
a second page buffer unit coupled to the second memory cell strings formed over different triple N well regions through the odd bit lines.
9. The NAND flash memory device of claim 8 , wherein the number of triple P well regions is a multiple of 2 or 3.