One transistor DRAM cell structure
View Patent ↗A one-transistor dynamic random access memory (DRAM) cell includes a transistor which has a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region. The first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region.
1. A one-transistor dynamic random access memory (DRAM) cell comprising:
a transistor having a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region, wherein the first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region,
wherein the first source/drain region includes a first silicide layer extending under the gate,
the second source/drain region includes a second silicide layer extending under the gate and a source/drain extension region extending under the gate,
wherein each of the first and second source/drain regions include a deep source/drain region and wherein the first source/drain region is devoid of a source/drain extension region.
2. The DRAM cell of claim 1 , wherein the second source/drain region includes an ohmic contact in series with the n-p diode junction.
3. The DRAM cell of claim 1 , wherein the Schottky diode junction with the body region is formed between the first silicide layer and the body region and the n-p diode junction with the body region is formed between the source/drain extension region and the body region.
4. The DRAM cell of claim 3 , wherein the body region has a first conductivity type and the source/drain extension region has a second conductivity type, different from the first conductivity type.
5. The DRAM cell of claim 1 , wherein the Schottky diode junction removes majority carriers from the body region to write a first state during a first write operation of the DRAM cell.
6. The DRAM cell of claim 5 , wherein when the transistor is characterized as an N-channel transistor, the majority carriers are removed from the body region in response to a potential at the first source/drain region being lower than a potential at the second source/drain region.
7. The DRAM cell of claim 5 , wherein when the transistor is characterized as a P-channel transistor, the majority carriers are removed from the body region in response to a potential at the first source/drain region being higher than a potential at the second source/drain region.
8. The DRAM cell of claim 1 , wherein when the transistor is characterized as an N-channel transistor, a stored value in the DRAM cell is sensed in response to a potential at the second source/drain region being lower than a potential at the first source/drain region.
9. The DRAM cell of claim 1 , wherein when the transistor is characterized as a P-channel transistor, a stored value in the DRAM cell is sensed in response to a potential at the second source/drain region being higher than a potential at the first source/drain region.
10. The DRAM cell of claim 1 , wherein the first silicide layer extending under the gate comprises a low-barrier silicide material for the majority carrier.
11. A one-transistor dynamic random access memory (DRAM) cell comprising:
a transistor having a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region, wherein the first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region and an ohmic contact in series with the n-p diode junction,
wherein the first source/drain region includes a first silicide layer extending under the gate,
the second source/drain region includes a second silicide layer extending under the gate and a source/drain extension region extending under the gate,
wherein each of the first and second source/drain regions include a deep source/drain region and wherein the first source/drain region is devoid of a source/drain extension region, and
wherein:
when the transistor is characterized as an N-channel transistor, the majority carriers are removed from the body region via the Schottky diode junction during a write operation of the DRAM cell in response to a potential at the first source/drain region being lower than a potential at the second source/drain region, and
when the transistor is characterized as a P-channel transistor, the majority carriers are removed from the body region via the Schottky diode junction during a write operation of the DRAM cell in response to a potential at the first source/drain region being higher than a potential at the second source/drain region.
12. The DRAM cell of claim 11 , wherein:
the Schottky diode junction with the body region is formed between the first silicide layer and the body region and the n-p diode junction with the body region is formed between the source/drain extension region and the body region.
13. The DRAM cell of claim 11 , wherein the first silicide layer is in physical contact with the body region and the second silicide layer is not in physical contact with the body region.
14. The DRAM cell of claim 11 , wherein:
when the transistor is characterized as an N-channel transistor, a stored value in the DRAM cell is sensed in response to a potential at the second source/drain region being lower than a potential at the first source/drain region, and
when the transistor is characterized as an P-channel transistor, a stored value in the DRAM cell is sensed in response to a potential at the second source/drain region being higher than a potential at the first source/drain region.
15. The DRAM cell of claim 11 , wherein the first silicide layer extending under the gate comprises a low-barrier silicide material for the majority carrier.