IP Library Granted Patent US 7,659,140
Granted Patent B2
US 7,659,140 · App. 11/694,933 · Granted Feb 9, 2010

Integrated circuit system with a debris trapping system

Assignee: Stats Chippac Ltd.
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Quick Facts
Patent No.
US 7,659,140
App. No.
11/694,933
Granted
Feb 9, 2010
Kind
B2
Abstract

An integrated circuit system including: providing an integrated circuit wafer having an integrated circuit side and a backside; mounting a protective adhesive on the integrated circuit side of the integrated circuit wafer; removing material from the backside of the integrated circuit wafer; and dicing the integrated circuit wafer through the protective adhesive to form an integrated circuit die.

Claims (57)

1. An integrated circuit system comprising:

providing an integrated circuit wafer having an integrated circuit side and a backside;

mounting a protective adhesive on the integrated circuit side of the integrated circuit wafer;

removing material from the backside of the integrated circuit wafer;

dicing the integrated circuit wafer through the protective adhesive to form an integrated circuit die; and

rolling a rolling system directly on the protective adhesive for removing the protective adhesive from the integrated circuit die.

2. The system as claimed in claim 1 wherein:

the mounting includes bonding the protective adhesive to the integrated circuit wafer.

3. The system as claimed in claim 1 further comprising:

removing the protective adhesive after dicing.

4. The system as claimed in claim 1 further comprising:

attaching the integrated circuit die with the protective adhesive mounted thereto to a substrate; and

removing the protective adhesive after attaching.

5. The system as claimed in claim 1 wherein:

the mounting the protective adhesive uses a transparent material.

6. An integrated circuit system comprising:

providing an integrated circuit wafer having an integrated circuit side and a backside;

bonding a protective adhesive tape on the integrated circuit side of the integrated circuit wafer;

preparing the integrated circuit wafer for grinding the backside thereof;

grinding material from the backside of the integrated circuit wafer;

preparing the integrated circuit wafer for dicing;

dicing the integrated circuit wafer through the protective adhesive tape to form an integrated circuit die; and

rolling a rolling system directly on the protective adhesive for removing the protective adhesive from the integrated circuit die including removing debris, formed by dicing the integrated circuit wafer, with the protective adhesive tape.

7. The system as claimed in claim 6 wherein:

the bonding laminates the protective adhesive tape under pressure.

8. The system as claimed in claim 6 further comprising:

removing the protective adhesive tape after dicing and before die attach.

9. The system as claimed in claim 6 further comprising:

attaching the integrated circuit die with the protective adhesive tape attached thereto to a substrate; and

removing the protective adhesive tape after attaching using the rolling system.

10. The system as claimed in claim 6 wherein the laminating process uses a transparent protective adhesive tape for dicing by a laser.

11. An integrated circuit system comprising:

a dicing debris trapping system for mounting a protective adhesive on an integrated circuit side of an integrated circuit wafer having an integrated circuit wafer having an integrated circuit side and a backside;

a system for removing material from the backside of the integrated circuit wafer;

a dicing system for dicing the integrated circuit wafer through the protective adhesive to form an integrated circuit die and

a rolling system for removing the protective adhesive from the integrated circuit die by rolling directly on the protective adhesive.

12. The system as claimed in claim 11 wherein:

the dicing debris trapping system is for bonding the protective adhesive to the integrated circuit wafer.

13. The system as claimed in claim 11 further comprising:

the rolling system is for removing the protective adhesive after dicing.

14. The system as claimed in claim 11 further comprising:

a pick-and-place system for attaching the integrated circuit die with the protective adhesive mounted thereto to a substrate; and

the rolling system for removing the protective adhesive after attaching.

15. The system as claimed in claim 11 wherein:

the dicing debris trapping system is for the mounting a transparent protective adhesive.

16. The system as claimed in claim 11 wherein:

the dicing debris trapping system is for bonding a protective adhesive tape on an integrated circuit side of an integrated circuit wafer having an integrated circuit side and a backside;

the system for removing material includes a system for preparing the integrated circuit wafer for grinding the backside thereof, the system for removing material is a grinding system for grinding material from the backside of the integrated circuit wafer;

the dicing system includes a system for preparing the integrated circuit wafer for dicing, the dicing system is for dicing the integrated circuit wafer through the protective adhesive tape to form an integrated circuit die; and

the rolling system for removing the protective adhesive tape includes debris, formed by the integrated circuit wafer diced, removed with the protective adhesive tape.

17. The system as claimed in claim 16 wherein:

the dicing debris trapping system is for laminating the protective adhesive tape to the integrated circuit wafer under pressure.

18. The system as claimed in claim 16 wherein:

the rolling system is for removing the protective adhesive tape after dicing and before die attach.

19. The system as claimed in claim 16 wherein:

the rolling system is for removing the protective adhesive tape after die attach.

20. The system as claimed in claim 16 wherein the dicing debris trapping system uses a transparent protective adhesive tape for dicing by a laser.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE NAME OF CONVEYING PARTY DATA FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC LTD. AND CORRECT THE NAME OF RECEIVING PARTY DATA FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED AT REEL: 64838 FRAME: 948. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 30, 2024
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 067637/0480 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 038378 FRAME: 0328 Recorded Aug 30, 2023
From: STATS CHIPPAC PTE. LTE.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064838/0948 →
RELEASE OF SECURITY INTEREST Recorded Jun 15, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052935/0327 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0328 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2007
From: LEE, TAEWOO; LEE, SANG-HO; YOON, BOHAN
To: STATS CHIPPAC LTD.
Reel/Frame 019098/0028 →
Continuity (1)
Related Publication 20080242053A1 · Oct 2, 2008