Design structure incorporating semiconductor device structures that shield a bond pad from electrical noise
View Patent ↗Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes active circuitry on a substrate, a bond pad carried by the substrate, and a shielding structure disposed between the substrate and the bond pad. The shielding structure includes a plurality of electrically characterized devices configured to reduce noise transmission from the active circuitry to the bond pad.
1. A design structure embodied in a readable storage device for designing, manufacturing, or testing a design, the design structure comprising:
a substrate;
active circuitry on the substrate;
a bond pad carried by the substrate; and
a shielding structure disposed between the substrate and the bond pad, the shielding structure including a plurality of capacitors configured to reduce noise transmission from the active circuitry to the bond pad, the plurality of capacitors arranged in a plurality of rows and a plurality of columns, each of the plurality of capacitors having a gate, and each of the plurality of rows having a contact region; and
a metallization level proximate to the substrate and disposed between the shielding structure and the bond pad, the metallization level including a plurality of first interconnection tabs arranged outside of an outer perimeter of the bond pad and a plurality of second interconnection tabs ananged outside of the outer perimeter of the bond pad, the first interconnection tabs and the second interconnection tabs arranged outside of the outer perimeter of the shielding structure, each of the plurality of first interconnection tabs physically and electrically coupled with the gate of the capacitor in one of the columns of capacitors, and each of the plurality of second interconnection tabs physically and electrically coupled with the contact region of one of the plurality of rows of the plurality of capacitors.
2. The design structure of claim 1 wherein the plurality of first interconnection tabs and the plurality of second interconnection tabs electrically couple a power supply through the one or more of the plurality of capacitors with the active circuitry on the substrate.
3. The design structure of claim 1 wherein the plurality of capacitors are planar capacitors.
4. The design structure of claim 1 wherein the design structure comprises a netlist, which describes the design.
5. The design structure of claim 1 wherein the design structure resides on storage device as a data format used for the exchange of layout data of integrated circuits.
6. The design structure of claim 1 wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.
7. The design structure of claim 1 wherein each of the plurality first interconnection tabs is electrically coupled with the gate of a respective one of the capacitors and each of the plurality of second interconnection tabs is electrically coupled with a power supply such that the plurality first interconnection tabs and the plurality of second interconnection tabs cooperate to electrically couple the power supply with the active circuitry.