IP Library › Granted Patent US 7,812,432
Granted Patent B2
US 7,812,432 · App. 12/268,591 · Granted Oct 12, 2010

Chip package with a dam structure on a die pad

Assignee: ChipMOS Technologies Inc.
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Quick Facts
Patent No.
US 7,812,432
App. No.
12/268,591
Granted
Oct 12, 2010
Kind
B2
Abstract

A chip package including a die pad, a plurality of leads, a chip, an adhesive, and a molding compound is provided. The die pad has a top surface and a bottom surface opposite to the top surface, wherein the die pad has a blocking portion disposed on the top surface, and the leads are disposed around the die pad. The chip is disposed on the top surface of the die pad surrounded by the blocking portion and is electrically connected to the leads. A top surface of the blocking portion is higher than the top surface of the die pad surrounded by the blocking portion. The adhesive is disposed between the chip and the die pad. The molding compound encapsulates the chip, a portion of the leads, and the die pad.

Claims (18)

1. A chip package, comprising:

a die pad having a top surface and a bottom surface opposite to the top surface, wherein the die pad has a blocking portion disposed on the top surface, and the blocking portion comprises a plurality of sub-blocking portions;

a plurality of leads disposed around the die pad;

a chip disposed on the top surface of the die pad surrounded by the blocking portion, wherein the chip is electrically connected to the leads, a top surface of the blocking portion is higher than the top surface of the die pad surrounded by the blocking portion;

an adhesive disposed between the chip and the die pad; and

a molding compound encapsulating the chip, a portion of the leads, and the die pad.

2. The chip package according to claim 1 , wherein the blocking portion comprises an annular blocking portion.

3. The chip package according to claim 1 , wherein the blocking portion comprises a plurality of strip-shaped sub-blocking portions and a plurality of L-shaped sub-blocking portions disposed distributedly.

4. The chip package according to claim 1 , wherein the die pad further comprises a groove located on the top surface of the die pad.

5. The chip package according to claim 1 , wherein the bottom surface of the die pad has a first opening and/or one end of at least one of the leads adjacent to the die pad has a second opening.

6. The chip package according to claim 1 , further comprising a plurality of first wires connecting the chip and one ends of the leads.

7. The chip package according to claim 6 , further comprising a plurality of second wires connecting the chip and the die pad.

8. The chip package according to claim 1 , wherein the adhesive is a conductive paste.

9. The chip package according to claim 8 , wherein the conductive paste comprises silver paste.

10. The chip package according to claim 1 , wherein a material of the molding compound is polymer.

11. The chip package according to claim 1 , wherein the blocking portion is formed integrally with the die pad through an etching process, and a material of the blocking portion is the same as a material of the die pad.

12. The chip package according to claim 1 , wherein the blocking portion is formed through an electroplating process and a material of the blocking portion is metal.

13. The chip package according to claim 1 , wherein the blocking portion is formed through dispensing and a material of the blocking portion is polymer.

Assignments (2)
RE-RECORD TO CORRECT THE EXECUTION DATE OF THE SECOND ASSIGNOR, PREVIOUSLY RECORDED ON REEL 021823 FRAME 0837. Recorded Apr 15, 2010
From: HOU, PO-KAI; SHIH, CHI-JIN
To: CHIPMOS TECHNOLOGIES INC.
Reel/Frame 024242/0514 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2008
From: HOU, PO-KAI; SHIH, CHI-JIN
To: CHIPMOS TECHNOLOGIES INC.
Reel/Frame 021823/0837 →
Priority Claims (1)
TW 97108075 A · Mar 7, 2008 · national
Continuity (1)
Related Publication 20090224384A1 · Sep 10, 2009