Formally deriving a minimal clock-gating scheme
View Patent ↗The present invention provides a fully automatic method for obtaining a circuit having minimized power consumption due to clock-gating. A circuit design to be optimized is modified to a reduced power modified design and associated with a clock gating scheme. Verification tools compare the modified design with the original design to a predetermined trigger-events to determine if the modified design can be used. Further modifications may be made iteratively until an optimal design is achieved.
1. A computer implemented method for implementing a clock gating scheme for at least one predefined section of logic comprised of a reference circuit design, wherein said reference circuit design is based on a predetermined reference clock gating scheme for said section of logic, characterised by the steps of:
a) defining a trigger event for at least one predefined section of logic comprised of said reference circuit design, which trigger event defines a cycle in which valid input data arrive at said logic section's input;
b) determining a latency time describing a propagation delay time for signal propagation between the input of said logic section and each output thereof;
c) deriving a new clock gating scheme for said logic section, which has a reduced number of clock activations for a predefined set of latches comprised of said circuit section, resulting in a respectively modified circuit design;
d) calculating, by the computer, relevant equivalence checking time points by adding said latency time to a time corresponding to said trigger event;
e) performing a formal verification based, sequential equivalence check of the outputs of said reference circuit design and said modified circuit design only at said relevant time points;
f) responsive to said sequential equivalence check indicating equivalent, defining said modified circuit design, which is associated with an improved clocking gating scheme than that one of said initial design, as a new reference design; and
g) repeating steps c) to e) until a predefined loop exit criterion is evaluated to TRUE.
2. The method according to claim 1 , wherein said trigger event is defined by a specific transition of signals that trigger the processing in the first stage of a pipeline within said section of logic.
3. The method according to claim 2 , wherein the source of said signals are a member of the group consisting of:
a) internal registers; and
b) external control inputs.
4. The method according to claim 3 , wherein said internal registers hold an internal state of a state machine, or delayed control signals, or data.
5. The method according to the claim 3 , wherein said external control inputs comprise any one of:
a) actual data inputs to the unit comprising said logic section, or
b) control signals in particular an instruction opcode.
6. The method according to claim 1 , wherein step c) is implemented by flipping inputs to predetermined registers in predetermined cycles.
7. The method according to claim 6 , wherein said flipping of inputs is implemented by inverting at least one of the inputs of said registers.
8. The method according to claim 7 , wherein said set of latches is maintained in a clock gating table, storing for each register the clock cycle number telling, when the clock activates the latch.
9. An electronic data processing system for implementing a clock gating scheme for at least one predefined section of logic comprised of a reference circuit design A, wherein said reference circuit design is based on a predetermined reference clock gating scheme for said section of logic, the electronic data process system configured to perform the method of:
a) defining a trigger event for at least one predefined section of logic comprised of said reference circuit design, which trigger event defines a cycle in which valid input data arrive at said logic section's input;
b) determining a latency time describing a propagation delay time for signal propagation between the input of said logic section and each output thereof;
c) deriving a new clock gating scheme for said logic section, which has a reduced number of clock activations for a predefined set of latches comprised of said circuit section, resulting in a respectively modified circuit design;
d) calculating relevant equivalence checking time points by adding said latency time to a time corresponding to said trigger event;
e) performing a formal verification based, sequential equivalence check of the outputs of said reference circuit design and said modified circuit design only at said relevant time points;
f) responsive to said sequential equivalence check indicating equivalent, defining said modified circuit design, which is associated with an improved clocking gating scheme than that one of said initial design, as a new reference design; and
g) repeating steps c) to e) until a predefined loop exit criterion is evaluated to TRUE.
10. The electronic data processing system according to claim 9 , wherein said trigger event is defined by a specific transition of signals that trigger the processing in the first stage of a pipeline within said section of logic.
11. The electronic data processing system according to claim 10 , wherein the source of said signals is a member of the group consisting of:
a) internal registers; and
b) external control inputs.
12. The electronic data processing system according to claim 11 , wherein said internal registers hold an internal state of a state machine, or delayed control signals, or data.
13. A computer program product for implementing a clock gating scheme for at least one predefined section of logic comprised of a reference circuit design, wherein said reference circuit design is based on a predetermined reference clock gating scheme for said section of logic,
the computer program product comprising a non-transitory computer useable medium including a computer readable program, wherein the computer readable program includes a functional component that when executed on a computer causes the computer to perform a method:
a) defining a trigger event for at least one predefined section of logic comprised of said reference circuit design, which trigger event defines a cycle in which valid input data arrive at said logic section's input;
b) determining a latency time describing a propagation delay time for signal propagation between the input of said logic section and each output thereof;
c) deriving a new clock gating scheme for said logic section, which has a reduced number of clock activations for a predefined set of latches comprised of said circuit section, resulting in a respectively modified circuit design;
d) calculating relevant equivalence checking time points by adding said latency time to a time corresponding to said trigger event;
e) performing a formal verification based, sequential equivalence check of the outputs of said reference circuit design and said modified circuit design only at said relevant time points;
f) responsive to said sequential equivalence check indicating equivalent, defining said modified circuit design, which is associated with an improved clocking gating scheme than that one of said initial design, as a new reference design; and
g) repeating steps c) to e) until a predefined loop exit criterion is evaluated to TRUE.
14. The method according to claim 13 , wherein said trigger event is defined by a specific transition of signals that trigger the processing in the first stage of a pipeline within said section of logic.
15. The method according to claim 12 , wherein the source of said signals is a member of the group consisting of:
a) internal registers; and
b) external control inputs.
16. The method according to claim 15 , wherein said internal registers hold an internal state of a state machine, or delayed control signals, or data.
17. The method according to the claim 15 , wherein said external control inputs comprise any one of:
a) actual data inputs to the unit comprising said logic section, or
b) control signals in particular an instruction opcode.
18. The method according to claim 14 , wherein step c) is implemented by flipping inputs to predetermined registers in predetermined cycles.
19. The method according to claim 18 , wherein said flipping of inputs is implemented by inverting at least one of the inputs of said registers.
20. The method according to claim 19 , wherein said set of latches is maintained in a clock gating table, storing for each register the clock cycle number telling, when the clock activates the latch.