Method for fabricating last level copper-to-C4 connection with interfacial cap structure
View Patent ↗The present invention relates to a method for fabricating a semiconductor device with a last level copper-to-C4 connection that is essentially free of aluminum. Specifically, the last level copper-to-C4 connection comprises an interfacial cap structure containing CoWP, NiMoP, NiMoB, NiReP, NiWP, and combinations thereof. Preferably, the interfacial cap structure comprises at least one CoWP layer. Such a CoWP layer can be readily formed over a last level copper interconnect by a selective electroless plating process.
1. A method comprising:
providing a semiconductor device that comprises a last level copper interconnect embedded in a last level dielectric layer, said last level copper interconnect is a fat wire;
forming an interfacial conductive cap structure that selectively covers the last level copper interconnect, wherein said interfacial conductive cap structure comprises CoWP, NiMoP, NiMoB, NiReP, NiWP, or combinations thereof;
forming a first dielectric cap layer over the interfacial conductive cap structure and the last level dielectric layer, wherein the first dielectric cap layer comprises silicon nitride and has a thickness ranging from about 100 Å to about 300 Å;
forming at least three additional dielectric cap layers over the first dielectric cap layer, which includes a silicon dioxide layer, a silicon nitride layer, and a photosensitive polyimide layer;
forming a via through the first dielectric cap layer and the at least three additional dielectric cap layers to expose the interfacial conductive cap structure, wherein the via is formed by first selectively removing a portion of the at least three additional dielectric cap layers to expose the first dielectric cap layer, and then selectively removing the exposed portion of the first dielectric cap layer, stopping at the interfacial conductive cap structure;
forming at least one ball-limiting metallurgy (BLM) layer in the via over the interfacial conductive cap structure; and
forming at least one controlled-collapse chip connection (C4) over the at least one BLM layer.
2. The method of claim 1 , wherein the interfacial conductive cap structure is essentially free of aluminum.
3. The method of claim 1 , wherein the interfacial conductive cap structure comprises a CoWP layer having a thickness ranging from about 200 Å to about 1000 Å.
4. The method of claim 1 , wherein the interfacial conductive cap structure is embedded in the first dielectric cap layer.
5. The method of claim 1 , wherein the last level copper interconnect, the interfacial conductive cap structure, the at least one BLM layer, and the at least one C4 connection form an electrically conductive path that extends through the first dielectric cap layer and the at least one additional dielectric cap layer.
6. The method of claim 1 , wherein the last level dielectric layer comprises fluorinated silica glass.
7. The method of claim 1 , wherein the interfacial conductive cap structure is formed by selective electroless plating.
8. The method of claim 1 , wherein the portion of the first dielectric cap layer is selectively removed by a pre-BLM sputter clean process.
9. A method comprising:
providing a semiconductor device that comprises a last level copper interconnect embedded in a last level dielectric layer;
forming an interfacial conductive cap structure that selectively covers the last level copper interconnect;
forming a first dielectric cap layer over the interfacial conductive cap structure and the last level dielectric layer;
forming at least three additional dielectric cap layers over the first dielectric cap layer, which include a silicon dioxide layer, a silicon nitride layer, and a photosensitive polyimide layer;
selectively removing a portion of said at least three additional dielectric cap layers to expose the first dielectric cap layer;
conducting in situ sputter cleaning, which selectively removes the exposed portion of the first dielectric cap layer, stopping at the at least one additional dielectric cap layer;
forming at least one ball-limiting metallurgy (BLM) layer over the interfacial conductive cap structure; and
forming at least one controlled-collapse chip connection (C4) over the at least one BLM layer.
10. The method of claim 9 , wherein the interfacial conductive cap structure is formed by selective electroless plating.
11. The method of claim 9 , wherein the interfacial conductive cap structure is essentially free of aluminum.
12. The method of claim 9 , wherein the interfacial conductive cap structure comprises a CoWP layer having a thickness ranging from about 200 Å to about 1000 Å.
13. The method of claim 9 , wherein the first dielectric cap layer comprises silicon nitride and has a thickness ranging from about 100 Å to about 300 Å.
14. The method of claim 9 , wherein the last level copper interconnect, the interfacial conductive cap structure, the at least one BLM layer, and the at least one C4 connection form an electrically conductive path that extends through the first dielectric cap layer and the at least one additional dielectric cap layer.
15. A method comprising:
providing a semiconductor device that comprises a last level copper interconnect embedded in a last level dielectric layer;
forming an interfacial conductive cap structure that selectively covers the last level copper interconnect, wherein said interfacial conductive cap structure comprises CoWP, NiMoP, NiMoB, NiReP, NiWP, or combinations thereof;
forming a first dielectric cap layer over the interfacial conductive cap structure and the last level dielectric layer;
forming at least one additional dielectric cap layer over the first dielectric cap layer;
forming a via through the first dielectric cap layer and the at least one additional dielectric cap layer to expose the interfacial conductive cap structure, wherein said forming said via includes selectively removing a portion of the at least one additional dielectric cap layer to expose the first dielectric cap layer, and then selectively removing the exposed portion of the first dielectric cap layer, stopping at the interfacial conductive cap structure;
forming at least one ball-limiting metallurgy (BLM) layer in the via over the interfacial conductive cap structure; and
forming at least one controlled-collapse chip connection (C4) over the at least one BLM layer.
16. The method of claim 15 wherein said selectively removing the exposed portion of the first dielectric cap layer comprises a pre-BLM sputter clean process.
17. A method comprising:
providing a semiconductor device that comprises a last level copper interconnect embedded in a last level dielectric layer;
forming an interfacial conductive cap structure that selectively covers the last level copper interconnect, wherein said interfacial conductive cap structure comprises CoWP, NiMoP, NiMoB, NiReP, NiWP, or combinations thereof;
forming a first dielectric cap layer over the interfacial conductive cap structure and the last level dielectric layer, wherein the first dielectric cap layer comprises silicon nitride and has a thickness ranging from about 100 Å to about 300 Å;
forming at least one additional dielectric cap layer over the first dielectric cap layer;
forming a via through the first dielectric cap layer and the at least one additional dielectric cap layer to expose the interfacial conductive cap structure, wherein said via is formed by first selectively removing a portion of the at least one additional dielectric cap layer to expose the first dielectric cap layer, and then selectively removing the exposed portion of the first dielectric cap layer, stopping at the interfacial conductive cap structure;
forming at least one ball-limiting metallurgy (BLM) layer in the via over the interfacial conductive cap structure; and
forming at least one controlled-collapse chip connection (C4) over the at least one BLM layer.
18. The method of claim 17 wherein said selectively removing the exposed portion of the first dielectric cap layer comprises a pre-BLM sputter clean process.