Hybrid orientation semiconductor structure with reduced boundary defects and method of forming same
View Patent ↗The present invention provides an improved amorphization/templated recrystallization (ATR) method for forming hybrid orientation substrates and semiconductor device structures. A direct-silicon-bonded (DSB) silicon layer having a (011) surface crystal orientation is bonded to a base silicon substrate having a (001) surface crystal orientation to form a DSB wafer in which the in-plane <110> direction of the (011) DSB layer is aligned with an in-plane <110> direction of the (001) base substrate. Selected regions of the DSB layer are amorphized down to the base substrate to form amorphized regions aligned with the mutually orthogonal in-plane <100> directions of the (001) base substrate, followed by recrystallization using the base substrate as a template. This optimal arrangement of DSB layer, base substrate, and amorphized region orientation provides a near-vertical, essentially defect-free boundary between original-orientation and changed-orientation silicon regions, thus enabling complete boundary region removal with smaller footprint shallow trench isolation than possible with ATR methods not so optimized.
1. A hybrid orientation substrate comprising:
a first silicon region having a (011) surface orientation coplanar with a second silicon region having a (001) surface orientation, wherein
said first and second silicon regions are disposed on a base substrate;
an in-plane <110> direction of the first silicon region is parallel to an in-plane <110> direction of the second silicon region;
edges of said first and second silicon regions are aligned with in-plane <100> directions of the second silicon region; and
said first and second silicon regions are separated by a near-vertical boundary in a boundary region.
2. The hybrid orientation substrate of claim 1 wherein said near-vertical boundary includes an angle within 15° of a vertical direction, and said edges of said first and second silicon regions are aligned within 10° of the in-plane <100> directions.
3. The hybrid orientation substrate of claim 1 wherein said base substrate is a bulk silicon-containing semiconductor material or a semiconductor-on-insulator having a (001) surface orientation.
4. The hybrid orientation substrate of claim 1 wherein said first and second silicon regions are silicon-containing materials selected from the group including Si, SiGe, SiC, SiGeC, and multilayered stacks thereof.
5. The hybrid orientation substrate of claim 1 further comprising a trench isolation region in said boundary region between said first and second silicon regions.
6. The hybrid orientation substrate of claim 1 further comprising buried insulating layers within at least one of said first and second silicon regions.
7. A semiconductor structure comprising:
a first silicon region having a (011) surface orientation coplanar with a second silicon region having a (001) surface orientation, wherein
said first and second silicon regions are disposed on a base substrate;
an in-plane <110> direction of the first silicon region is parallel to an in-plane <110> direction of the second silicon region;
edges of said first and second silicon regions are aligned with in-plane <100> directions of the second silicon region;
said first and second silicon regions are separated by a boundary region;
a first device of a first conductivity located upon said first silicon region; and
a second device of a second conductivity that differs from the first conductivity located upon said second silicon region.
8. The semiconductor structure of claim 7 wherein said boundary region includes an angle within 15° of a vertical direction, and said edges of said first and second silicon regions are aligned within 10° of the in-plane <100> directions.
9. The semiconductor structure of claim 7 wherein said base substrate is a bulk silicon-containing semiconductor material or a semiconductor-on-insulator having a (001) surface orientation.
10. The semiconductor structure of claim 7 wherein said first and second silicon regions are silicon-containing materials selected from the group including Si, SiGe, SiC, SiGeC, and multilayered stacks thereof.
11. The semiconductor structure of claim 7 wherein said boundary region comprises a trench isolation region.
12. The semiconductor structure of claim 7 further comprising buried insulating layers within at least one of said first and second silicon regions.
13. The semiconductor structure of claim 7 wherein said first device is a p-channel field effect transistor (pFET) and said second device is an n-channel field effect transistor (nFET).