Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation
View Patent ↗A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.
1. A wiring structure of a semiconductor device comprising:
a wiring layer having an upper surface and a lower surface;
an upper plug formed in a first insulating layer above the upper surface of the wiring layer;
a lower plug formed in a second insulating layer below the lower surface of the wiring layer and opposite to the upper plug with the wiring layer interposed; and
at least one cap layer interposed between the wiring layer and any one of the upper plug and the lower plug and positioned below any one of a plane defined by a substantial portion of the upper surface and a plane defined by a substantial portion of the lower surface, respectively,
wherein, in a case that there is a single grain in a first region of the wiring layer between the upper plug and the lower plug, a size of the grain in the first region is substantially equal to a single grain in a second region of the wiring layer not between the upper plug and the lower plug and, in case that there are a number of grains in the first region, average size of the grains in the first region is substantially equal to the single grain in the second region.
2. The wiring structure according to claim 1 , wherein the second region of the wiring layer is between the first insulating layer and the second insulating layer.
3. The wiring structure according to claim 1 , wherein the second region of the wiring layer is between a different upper plug from the upper plug and a different lower plug from the lower plug.
4. The wiring structure according to claim 1 , wherein the wiring layer has a substantially continuous distribution of grains from the first region to the second region.
5. The wiring structure according to claim 1 , wherein no void is formed between the first region and the second region.
6. The wiring structure according to claim 1 , wherein the wiring layer, the upper plug and the lower plug are made of the same material.
7. The wiring structure according to claim 1 , wherein the at least one cap layer is formed of a first cap layer formed on the wiring layer upper surface below the upper plug and a second cap layer different from the first cap layer formed on the wiring layer upper surface below the first insulating layer.
8. The wiring structure according to claim 1 , wherein the at least one cap layer is formed of a first cap layer formed continuously on the wiring layer upper surface below the upper plug and the first insulating layer and a second cap layer different from the first cap layer formed on the first cap layer below the upper plug.
9. The wiring structure according to claim 1 , wherein the at least one cap layer is a continuous layer formed on the wiring layer upper surface below the upper plug and below the first insulating layer.
10. The wiring structure according to claim 1 , wherein the at least one cap layer comprises:
a first cap layer interposed between the wiring layer and the upper plug and positioned below the plane defined by the substantial portion of the upper surface;
a second cap layer interposed between the wiring layer and the lower plug and positioned below the plane defined by the substantial portion of the lower surface.