Regulator having interleaved latches
A charge pump system ( 100 ) includes a charge pump ( 102 ), and a regulator ( 101 ) that includes a clock generator ( 120 ) for providing a clock signal, a control logic ( 130 ) coupled to the clock generator, and a comparator ( 140 ) coupled to an output of the charge pump. The comparator includes a plurality of interleaved latches ( 211, 212, 213 and 214 ) driven by a single differential ( 203 ) stage that compares the output voltage and a reference voltage. The control logic provides timing signals to cause each latch to perform a latch action at different points in time within each period of the clock signal, each point in time equally spaced apart. An output from each latch is coupled to an output stage ( 205 ). An output signal from the output stage regulates an output voltage from the charge pump. In one embodiment, the charge pump is coupled to a flash memory ( 190 ).
1. A charge pump system, comprising:
a charge pump having an input for receiving a clock signal, another input for receiving an input voltage, and an output for providing an output voltage; and
a regulator for regulating the output voltage, the regulator comprising:
a reference voltage terminal for providing a reference voltage; and
a comparator having a first input coupled to the reference voltage terminal, a second input coupled to the output of the charge pump, and an output, the comparator including:
a differential stage, the differential stage having an input coupled to the reference voltage terminal, another input coupled to the output of the charge pump, and an output,
a control logic for providing a plurality of secondary clock signals derived from the clock signal, each secondary clock signal phase shifted from the clock signal and from other secondary clock signals,
a plurality of interleaved latches, each latch having an input coupled to the output of the differential stage, one latch of the plurality of interleaved latches having a clock input for receiving the clock signal, each of the other latches of the plurality of interleaved latches having a clock input for receiving one of the secondary clock signals, each latch having an output, and
an output stage having a plurality of inputs, each coupled to the output of each latch, the output stage providing an enable signal to the charge pump in response to outputs of the plurality of latches.
2. The charge pump system of claim 1 , wherein the outputs of the plurality of latches are responsive to a value of the output voltage of the charge pump relative to the value of the reference voltage.
3. The charge pump system of claim 2 , wherein each secondary clock signal is phase shifted from the clock signal and from the other secondary clock signals by a same amount of phase shift.
4. The charge pump system of claim 3 , wherein each secondary clock signal is phase shifted by 360/n degrees from the clock signal and from other secondary clock signals, where n is a number of latches in the plurality of latches.
5. The charge pump system of claim 1 , further comprising a voltage translation circuit coupled between the output of the charge pump and the second input of the comparator, the voltage translation circuit reducing values of the output voltage provided by the charge pump.
6. The charge pump system of claim 5 , further comprising a load coupled to the output of the charge pump, wherein the load includes a capacitance.
7. The charge pump system of claim 1 , wherein the output of each latch provides, at different times, an indication that an output voltage of the charge pump is above or below a target value for the output voltage.
8. The charge pump system of claim 7 , wherein each latch is clocked by one of the plurality of secondary clock signals once within each cycle of the clock signal and at a different point in time from points in time that the other latches are clocked.
9. The charge pump system of claim 1 , wherein each latch is capable of a pre-charge action, an isolation action, and a latch action, wherein each latch performs the latch action during a different portion of a period of the clock signal.
10. The charge pump system of claim 1 , wherein after detection of an overshoot of the output voltage of the charge pump above a target value, the differential stage changes its output.
11. The charge pump system of claim 10 , wherein after detection of an overshoot of the charge pump above the target value, the regulator provides a signal to disable operation of the charge pump.
12. The charge pump system of claim 1 , wherein after detection of an undershoot of the output voltage of the charge pump below a target value, the differential stage changes its output.
13. The charge pump system of claim 12 , wherein after detection of an undershoot of the charge pump below the target value, the regulator provides a signal to enable operation of the charge pump.
14. A regulator for a charge pump comprising:
a single comparison circuit for comparing a reference voltage and a present value of an output voltage of the charge pump, the single comparison circuit having at least one output responsive to a comparison;
a plurality of interleaved latches, coupled to the single comparison circuit, each latch having at least one input coupled to the at least one output of the single comparison circuit, each latch capable of a pre-charge action, an isolation action, and a latch action, each latch having an output, wherein each latch performs a latch action at a different point in time from points in time that other latches perform a latch action, and wherein outputs of the latches are responsive to the output of the single comparison circuit at a different points in time; and
an output stage having an plurality of inputs and having an output, the output of each latch coupled to one input of the plurality of inputs of the output stage, the output of the output stage coupled the charge pump, wherein the output of the output stage regulates an output voltage of the charge pump.
15. The regulator of claim 14 , wherein the output stage consists of one of: an OR gate, an AND gate, a NOR gate and a NAND gate.
16. An integrated circuit, comprising:
a charge pump including a regulator, the regulator comprising:
a single differential circuit coupled to the charge pump for comparing an output of the charge pump and a reference value;
a plurality of interleaved latches, each latch coupled to the at least one output of the single differential circuit, each latch capable of a pre-charge action, an isolation action, and a latch action, each latch having an output coupled to the charge pump, wherein each latch performs an action at a different point in time from points in time that other latches perform the same action, and wherein outputs of the latches are responsive to the output of the single differential circuit at a different points in time; and
a control logic, coupled to a clock generator and to each latch, for providing timing signals to each latch, such that operation of the plurality of latches is interleaved,
wherein outputs from the plurality of latches regulate operation of the charge pump.
17. The integrated circuit of claim 16 , wherein the timing signals cause each latch to perform the isolation action during a different portion of a period of the clock signal.
18. The integrated circuit of claim 17 , wherein the timing signals cause each latch to perform the latch action during a different portion of the period of the clock signal.
19. The integrated circuit of claim 16 , wherein the charge pump includes an output for providing an output voltage, and wherein the outputs from the plurality of latches regulate a value of the output voltage of the charge pump.
20. The integrated circuit of claim 16 , including a flash memory, wherein the output voltage of the charge pump writes to the flash memory.