IP Library Granted Patent US 7,956,460
Granted Patent B2
US 7,956,460 · App. 11/794,243 · Granted Jun 7, 2011

Semiconductor chip and method for manufacturing same, electrode structure of semiconductor chip and method for forming same, and semiconductor device

Assignee: Rohm Co., Ltd.
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Quick Facts
Patent No.
US 7,956,460
App. No.
11/794,243
Granted
Jun 7, 2011
Kind
B2
Abstract

A semiconductor chip according to the present invention includes a semiconductor substrate, a bump of a metal projecting from a surface of the semiconductor substrate, and an alloy film covering the entire surface of the bump, the alloy film being composed of an alloy of the metal of the bump and a second metal.

Claims (23)

1. A semiconductor device comprising:

a first semiconductor chip having:

a first semiconductor substrate, a multilevel interconnection structure being provided on a surface of the first semiconductor substrate, an uppermost interconnection layer in the multilevel interconnection structure being partly exposed as a pad from an opening formed in a surface protective film;

a first bump of a metal projecting from a surface of the first semiconductor substrate, the first bump covering the opening and projecting from a surface of the surface protective film; and

a first alloy film covering an entire surface of the first bump, the first alloy film being composed of an alloy of the metal of the first bump and a second metal; and

a second semiconductor chip having:

a second semiconductor substrate, a multilevel interconnection structure being provided on a surface of the second semiconductor substrate, an uppermost interconnection layer in the multilevel interconnection structure being partly exposed as a pad from an opening formed in a surface protective film;

a second bump of a metal projecting from a surface of the second semiconductor substrate, the second bump covering the opening and projecting from a surface of the surface protective film; and

a second alloy film covering an entire surface of the second bump, the second alloy film being composed of an alloy of the metal of the second bump and a third metal; and

wherein the first bump is made of the same material as that of the second bump,

wherein the second alloy film is made of the same material as that of the second alloy film, and

wherein the first and second semiconductor chips are bonded to each other with an active surface of the first semiconductor chip being opposed to an active surface of the second semiconductor chip.

2. A semiconductor device as set forth in claim 1 , wherein a resin layer is interposed between the first and second semiconductor chips.

3. A semiconductor device as set forth in claim 2 , wherein the resin layer is an anisotropic conductive film.

4. A semiconductor device as set forth in claim 1 , wherein the first semiconductor chip has an external connection pad provided on a peripheral portion thereof, and the external connection pad is electrically connected to a lead portion of a lead frame via a bonding wire.

5. A semiconductor device as set forth in claim 4 , wherein the first semiconductor chip, a first part of the lead portion of the lead frame and the bonding wire are sealed in a sealing resin to provide a semiconductor package.

6. A semiconductor device as set forth in claim 5 , wherein a second part of the lead portion of the lead frame is exposed from the sealing resin to function as an external connection portion.

7. A semiconductor device manufacturing method comprising:

a bump forming step of forming a bump of a metal projecting from a surface of a semiconductor substrate;

a metal film forming step of forming a metal film made of a second metal capable of making an alloy with the metal of the bump on an entire surface of the semiconductor substrate on which the bump is formed;

an alloying step of heat-treating the semiconductor substrate to form an alloy of the metal of the bump and the second metal of the metal film after the metal film forming step;

a step of removing a portion of the metal film that is not alloyed by etching after the alloying step; and

a step of bonding two semiconductor chips each manufactured through the preceding steps.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2020
From: ACHLYS TECHNOLOGIES INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 052957/0699 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2020
From: ROHM CO., LTD.
To: ACHLYS TECHNOLOGIES INC.
Reel/Frame 052273/0877 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2007
From: NAKATANI, GORO
To: ROHM CO., LTD.
Reel/Frame 019535/0465 →
Priority Claims (2)
JP 2004-381363 · Dec 28, 2004 · national
JP 2005-129000 · Apr 27, 2005 · national
Continuity (1)
Related Publication 20080017982A1 · Jan 24, 2008