Material removing processes in device formation and the devices formed thereby
Devices having voids are producible by employing an electrochemical corrosion process. For example, an electrically conductive region is formed to have a surrounding chemically distinct region. Such formation is possible through conventional semiconductor processing techniques such as a copper damascene process. The surrounded conducting material is configured to be in electrical communication with a charge separation structure. The electrically conducting region is contacted with a fluid electrolyte and electromagnetic radiation is made to illuminate the charge separation region to induce separation of electrons and holes. The resulting separated charges are used to drive an electrochemical corrosion process at the conductive material/electrolyte interface resulting in the removal of at least a portion of the electrically conducting material. The induced corrosion leaves a void that is useful, for example, as a highly effective dielectric in integrated circuits, functions to allow component separation such as gear separation in microelectromechanical devices or produces long cavities useful for material separation analogous to the distillation columns used in liquid chromatography.
1. A process for fabricating a device comprising:
forming conductive regions on a semiconductor substrate, said conductive regions being located within or surrounded by a dielectric material; electrically connecting at least a portion of said conductive regions to a charge separation structure;
allowing electromagnetic radiation to be incident on said charge separation structure to produce an electrical current between said conductive regions and said charge separation structure; and
allowing a fluid electrolyte to contact said conductive regions such that a portion of said at least portion of said conductive regions electrically connected to said charge separation structure is removed to produce a void of having a volume of at least 1000 nm 3 , whereby said void functions as an operative structure of said device.
2. The process of claim 1 wherein said operative function comprises a dielectric region that attenuates high frequency rf interactions.
3. The process of claim 2 wherein said void is positioned between two of said conductive regions.
4. The process of claim 1 wherein said operative function comprises a chromatographic column.
5. The process of claim 1 wherein said device comprises an integrated circuit.
6. The process of claim 1 wherein said device comprises a MEMS device.
7. The process of claim 1 wherein said conductive regions comprise copper.
8. The process of claim 1 wherein said conductive regions comprise aluminum.
9. The process of claim 1 wherein said dielectric material comprises silicon oxide.
10. The process of claim 1 wherein said semiconductor substrate comprises silicon.
11. A process of forming a MEMS device on a substrate comprising:
forming conductive regions within a dielectric material about a MEMS component connecting said conductive regions to a charge separation structure;
contacting said conductive regions with an electrolyte, and allowing light to be incident on said charge separation structure whereby said conductive regions are removed by electrochemical corrosion thereby releasing said MEMS component.
12. The process of claim 11 wherein a void suitable for chromatographic procedures is formed between two of said conducting regions.
13. The process of claim 12 wherein the charge separation structure remains in said MEMS device as a source of charge for electrophoretic procedures.
14. The process of claim 11 wherein an external power supply rather than said charge separation structure is electrically connected with said conductive regions and drives said electrochemical corrosion.
15. The process of claim 11 wherein said MEMS component is a gear or mirror.
16. The process of claim 11 wherein said substrate comprises silicon.
17. A silicon integrated circuit comprising a substrate comprising silicon, a plurality of transistors, a plurality of conducting regions electrically connecting said transistors and a void positioned between two of said conducting regions whereby high frequency interaction between signals in said two of said conducting regions is attenuated.
18. The integrated circuit of claim 17 wherein said conducting region comprises copper.