System and method for programming cells in non-volatile integrated memory devices
A system and method for quickly and efficiently programming hard-to-program storage elements in non-volatile integrated memory devices is presented. A number of storage elements are simultaneously subjected to a programming process with the current flowing through the storage elements limited to a first level. As a portion of these storage elements reach a prescribed state, they are removed from the set of cells being programmed and the current limit on the elements that continue to be programmed is raised. The current level in these hard-to-program cells can be raised to a second, higher limit or unregulated. According to another aspect, during a program operation the current limit allowed for a cell depends upon the target state to which it is to be programmed.
1. A non-volatile memory comprising:
an array of multi-state storage elements connected in one or more columns along bit lines and along one or more rows connected to word lines;
programming circuitry connectable to the bit lines and the word lines to apply a set of voltages to program one or more selected storage elements along a first word line each to a corresponding target one of said multi-states during a programming process, the set of voltages including a series of one or more programming pulses applied to the first word line; and
current limiting circuitry connectable to said bit lines to limit the current through the bit lines, whereby the current through a first of the selected storage elements is limited to not exceed a value dependent upon the first selected storage element's corresponding target state during the programming process, said value being set independently of the current limit value of the other bit lines and prior to applying the first of the programming pulses.
2. The non-volatile memory of claim 1 , wherein said set of voltages includes applying a source-drain voltage difference dependent upon the selected target state.
3. The non-volatile memory of claim 1 , wherein the storage elements are charge-storing devices.
4. The non-volatile memory of claim 3 , wherein the storage elements are floating gate transistors.
5. In a non-volatile memory including an array of multi-state storage elements connected in one or more columns along bit lines and along one or more rows connected to word lines, a method of programming one or more selected storage elements along a first word line each to a corresponding target one of said multi-states during a programming process, comprising:
applying a set of voltages to program the selected storage elements each to a corresponding target one of said multi-states by programming circuitry connectable to the bit lines and the word lines, the set of voltages including a series of one or more programming pulses applied to the first word line; and
prior to applying the first of the programming pulses, limiting the current through the bit lines by circuitry connectable to said bit lines, whereby the current through a first of the selected storage elements is limited to not exceed a value dependent upon the first selected storage element's corresponding target state during the programming process, said value being set independently of the current limit value of the other bit lines.
6. The method of claim 5 , wherein said applying a set of voltages includes applying a source-drain voltage difference dependent upon the selected target state.
7. The method of claim 5 , wherein the storage elements are charge-storing devices.
8. The method of claim 7 , wherein the storage elements are floating gate transistors.