Method for manufacturing a FinFET device comprising a mask to define a gate perimeter and another mask to define fin regions

1. A method for manufacturing a FinFET device, comprising:

providing a substrate having a mask disposed thereon;

covering portions of the mask to define a perimeter of a gate region;

removing uncovered portions of the mask to expose the substrate;

covering a part of the exposed substrate with another mask to define at least one fin region;

forming the at least one fin and the gate region through both masks and the substrate, the gate region having side walls;

disposing insulating layers around the at least one fin and onto the side walls;

disposing a conductive material into the gate region and onto the insulating layers to form a gate electrode;

covering parts of the mask adjacent to ends of the at least one fin, to define source and drain regions;

removing uncovered parts of the mask;

removing the remaining parts of the mask to produce an intermediate structure;

disposing insulating spacers around perimeters of the intermediate structure, and then

forming a source and a drain in the source and drain regions.

2. The method as claimed in claim 1 , wherein the gate region is a T-shaped region.

3. The method as claimed in claim 1 , wherein the mask is a hard mask.

4. The method as claimed in claim 3 , further comprising planarizing the conductive material to be approximately coplanar with the hard mask.

5. The method as claimed in claim 1 , wherein the mask consists essentially of Silicon Nitride (S 3 N 4 ).

6. The method as claimed in claim 1 , wherein said step of disposing a conductive material further comprises disposing the conductive material onto three surfaces of the at least one fin.

7. The method as claimed in claim 1 , wherein the substrate is a semiconductor-on-insulator substrate.

8. The method as claimed in claim 1 , wherein the substrate comprises silicon.

9. The method as claimed in claim 1 , wherein the insulating layers consist essentially of high-k dielectric layers.

10. The method as claimed in claim 1 , wherein the conductive material comprises a material selected from the group consisting of TaN, and TiN.

11. The method as claimed in claim 1 , wherein each of the insulating layers comprise a material selected from the group consisting of Silicon Oxynitride (SiON), oxides of silicon, Silicon Nitride (Si 3 N 4 ), Hafnium Dioxide (HfO 2 ), Zirconium Dioxide (ZrO 2 ), Aluminum Oxide (Al 2 O 3 ), and Hafnium Silicate (HfSiO 4 ).

12. The method as claimed in claim 1 , wherein the another mask is a photoresist mask.

13. The method as claimed in claim 1 , further comprising forming the source and the drain by implanting dopants into the source and drain regions.

14. The method as claimed in claim 13 , further comprising forming the insulating spacers around external perimeters of the source and drain regions and the gate region.

15. A method for making a FinFET device, comprising:

providing a silicon-on-insulator substrate having a hard mask disposed over the silicon-on-insulator substrate;

covering portions of the hard mask with a photoresist material to define a perimeter of a gate region;

removing uncovered portions of the hard mask to expose the silicon on the insulator;

covering a part of the silicon on the insulator to define at least one fin;

forming the gate region and the at least one fin in the gate region through the silicon on the insulator, the gate region having silicon side walls;

forming insulating layers on the at least one fin and the silicon side walls;

disposing a conductive material into the gate region and onto the insulating layers;

covering parts of the hard mask adjacent to ends of the at least one fin, to define source and drain regions;

removing uncovered parts of the hard mask and the silicon on the insulator;

removing the remaining parts of the hard mask to produce an intermediate structure;

disposing insulating spacers around perimeters of the intermediate structure, and forming a source and a drain in the source and drain regions.

16. The method as claimed in claim 15 , further comprising forming silicides in parts of the source and drain regions.

17. The method as claimed in claim 15 , further comprising planarizing the conductive material.

18. The method as claimed in claim 15 , further comprising chemically mechanically polishing the conductive material to be substantially planar with the hard mask.

19. The method as claimed in claim 15 , wherein said step of forming the source and the drain comprising implanting dopants into the source and drain regions.