Electronic device including doped regions between channel and drain regions and a process of forming the same
An electronic device can include a drain region of a transistor, wherein the drain region has a first conductivity type. The electronic device can also include a channel region of the transistor, wherein the channel region has a second conductivity type opposite the first conductivity type. The electronic device can further include a first doped region having the first conductivity type, wherein the first doped region extends from the drain region towards the channel region. The electronic device can still further include a second doped region having the first conductivity type, wherein the second doped region is disposed between the first doped region and the channel region.
1. An electronic device comprising:
a drain region of a transistor, wherein the drain region has a first conductivity type;
a channel region of the transistor, wherein the channel region has a second conductivity type opposite the first conductivity type;
a first doped region having the first conductivity type, wherein the first doped region extends from the drain region towards the channel region; and
a second doped region having the first conductivity type, wherein the second doped region is disposed between the first doped region and the channel region,
wherein the first doped region has a peak dopant concentration lower than peak dopant concentrations of the drain region and the second doped region.
2. The electronic device of claim 1 , wherein each of the first doped region and the second doped region lie along a primary surface of a semiconductor layer.
3. The electronic device of claim 1 , wherein the second doped region has a width that is at least 0.11 times the depth of the first doped region.
4. The electronic device of claim 3 , wherein the second doped region has a width that is no greater than approximately 5 times the depth of the first doped region.
5. The electronic device of claim 1 , wherein the second doped region has a width that is in a range of approximately 0.3 to approximately 2 times a depth of the first doped region.
6. The electronic device of claim 1 , wherein a width of the second doped region is no greater than approximately 0.5 times a width of the first doped region.
7. The electronic device of claim 6 , wherein the width of the second doped region is at least approximately 0.05 times the width of the first doped region.
8. The electronic device of claim 1 , wherein the second doped region has a width no greater than approximately 0.3 micron.
9. The electronic device of claim 8 , wherein the second doped region has a width of at least approximately 0.05 micron.
10. The electronic device of claim 1 , wherein a peak dopant concentration of the second doped region is lower than a peak dopant concentration of the drain region.
11. The electronic device of claim 1 , wherein a peak dopant concentration of the second doped region is no greater than approximately 9 times a peak dopant concentration of the first doped region.
12. The electronic device of claim 1 , wherein a peak dopant concentration of the second doped region is in a range of approximately 2 to approximately 5 times a peak dopant concentration of the first doped region.
13. The electronic device of claim 1 , further comprising a gate electrode and a conductive electrode, wherein:
the gate electrode and the conductive electrode are separated by a distance; and
a width of the first doped region is no greater than approximately 1.5 times the distance.
14. A process of forming an electronic device comprising:
forming a drain region of a transistor, wherein the drain region is formed along a primary surface of a semiconductor layer and has a first conductivity type;
forming a first doped region along the primary surface and having the first conductivity type;
forming a second doped region along the primary surface and having the first conductivity type; and
forming a gate electrode of the transistor after forming the second doped region, wherein a channel region of the transistor is disposed under the gate electrode and along the primary surface and has a second conductivity type opposite the first conductivity type,
wherein after forming the drain region, first doped region, second doped region, and the gate electrode:
the first doped region is disposed between the drain region and the second doped region; and
the second doped region is disposed between the first doped region and the channel region.
15. The process of claim 14 , further comprising:
forming a first spacer; and
removing the first spacer,
wherein forming the second doped region is performed such that the second doped region is within the semiconductor layer at a location below where the first spacer was removed.
16. The process of claim 15 , further comprising:
forming a first layer over the primary surface;
patterning the first layer to define a first layer opening;
forming a second layer over the primary surface after forming the first spacer; and
removing portions of the second layer that overlie the first layer, wherein removing portions is performed before removing the first spacer.
17. The process of claim 16 , wherein forming the spacer comprises:
forming a first spacer layer over the first layer and within the first layer opening; and
anisotropically etching the first spacer layer to form the first spacer.
18. The process of claim 16 , wherein:
the first layer has a composition different from the first sidewall spacer and the second layer; and
the second layer has a composition different from the first sidewall spacer.
19. The process of claim 16 , further comprising:
forming a third layer over the primary surface before forming the first layer;
patterning the third layer to define a third layer opening; and
forming a second sidewall spacer before forming the first sidewall spacer.
20. The process of claim 19 , wherein:
the first layer has a composition different from the first sidewall spacer, the second layer, and the third layer;
the second layer has a composition different from the first sidewall spacer, the second sidewall spacer, and the third layer;
the third layer has a composition different from the first sidewall spacer; and
the first sidewall spacer has a composition different from the second sidewall spacer.
21. The process of claim 19 , wherein:
each of the first layer and the second sidewall spacer includes a nitride;
the second layer includes an organic resist material;
the third layer includes an oxide; and
the first sidewall spacer includes amorphous silicon or polycrystalline silicon.
22. The process of claim 15 , wherein a width of the second doped region and a width of the first sidewall spacer at its base are substantially equal.
23. The process of claim 14 , wherein:
forming the first doped region includes implanting a first dopant into the semiconductor layer; and
forming the second doped region includes implanting a second dopant into a portion of the first doped region.
24. The process of claim 23 , wherein forming the second doped region is performed at a dose in a range of approximately 2×10 12 ions/cm 2 to approximately 2×10 13 ions/cm 2 .