Devices with gate-to-gate isolation structures and methods of manufacture

1. A method, comprising:

forming a plurality of trenches in a pad film to form raised portions;

depositing a hard mask in the trenches and over the raised portions of the pad film;

forming a plurality of fins comprising the raised portions and a second plurality of fins comprising the hard mask deposited in the trenches, each of which are separated by a deep trench;

removing the hard mask on the plurality of fins comprising the raised portions and the second plurality of fins resulting in a dual height fin array; and

forming gate electrodes within each deep trench between each fin of the dual height fin array, burying the second plurality of fins and abutting sides of the plurality of fins comprising the raised portions,

wherein the plurality of fins comprising the raised portions electrically and physically isolate adjacent gate electrode of the gate electrodes.

2. The method of claim 1 , wherein the pad film is formed on an underlying substrate of BULK wafer.

3. The method of claim 1 , wherein the pad film is formed on an underlying substrate of Silicon on Insulator (SOI), and each deep trench is formed by etching to an insulator layer of the SOI.

4. The method of claim 1 , wherein the pad film is deposited on an underlying substrate and the deep trenches are formed in the pad film, hard mask and portion of an underlying substrate.

5. The method of claim 4 , wherein the pad film is SiO 2 and Si 3 N 4 .

6. The method of claim 4 , wherein the pad film is SiO 2 .

7. The method of claim 1 , wherein the raised portion raises the plurality of fins to a height higher than the second plurality of fins.

8. The method of claim 1 , wherein the plurality of fins have a width of about 10 nm.

9. The method of claim 1 , wherein the plurality of fins have uniform spacing therebetween in a regular pattern.

10. The method of claim 1 , wherein the adjacent gate electrodes are formed by deposition and etching processes.

11. The method of claim 10 , wherein the etching of the adjacent gate electrodes is to a level lower than the plurality of fins.

12. The method of claim 1 , wherein the plurality of fins is at a sufficient height to isolate adjacent gate electrodes at a minimum image.

13. A method comprising:

forming a first pad film on a substrate;

etching trenches in the first pad film, stopping before the substrate, to form raised portions of the first pad film;

forming a hard mask in the trenches and over the raised portions;

forming a plurality of trenches into the first pad film, the hard mask and the substrate, creating an array of fins comprising:

first fins composed of the raised section, the hard mask and the substrate; and

second fins composed of the first pad film, the hard mask in the trenches and the substrate,

removing the hard mask on the first fins and the second fins, resulting in a dual height array of fins, wherein the first fins are higher than the second fins; and

forming gate electrodes within each trench of the plurality of trenches, between each fin of the dual height array of fins, which bury the second fins and abut sides of the first fins,

wherein the first fins comprising the raised portions electrically and physically isolate adjacent gate electrode of the gate electrodes.

14. The method of claim 13 , wherein the substrate is a BULK wafer.

15. The method of claim 13 , wherein the substrate is a Silicon on Insulator (SOI), and each trench is formed by etching to an insulator layer of the SOI.

16. The method of claim 13 , the hard mask is Si 3 N 4 and the film is SiO 2 for subsequent selective etching processes.

17. The method of claim 13 , wherein the first fins comprising the raised portions have a width of about 10 nm.

18. The method of claim 13 , wherein the adjacent gate electrodes are faulted by deposition and etching processes.

19. The method of claim 13 , wherein the first fins are at a sufficient height to isolate adjacent gate electrodes at a minimum image.