Method for forming P-type lightly doped drain region using germanium pre-amorphous treatment
View Patent ↗A method for forming a MOS device with an ultra shallow lightly doped diffusion region includes providing a gate dielectric layer overlying a substrate surface region, forming a gate structure overlying the gate dielectric layer, performing a first implant process using a germanium species to form an amorphous region within an LDD region using the gate structure as a mask, and performing a second implant process in the LDD region using a P-type impurity and a carbon species. A first thermal process activates the P-type impurity in the LDD region, forming side wall spacers overlying the gate structure, and performing a third implant process using a first impurity to form active source/drain regions in a vicinity of the surface region adjacent to the gate structure using the gate structure and the spacers as a mask. A second thermal process then activates the first impurity in the active source/drain regions.
1. A method for forming a MOS device with an ultra shallow lightly doped diffusion region, the method comprising:
providing a semiconductor substrate including a surface region;
providing a gate dielectric layer overlying the surface region;
forming a gate structure overlying a portion of the gate dielectric layer;
performing a first implant process using a germanium species to form an amorphous region within a lightly doped drain region in the semiconductor substrate using the gate structure as a mask;
performing a second implant process in the lightly doped drain region using a P type impurity and a carbon species using the gate structure as a mask;
performing a first thermal process to activate the P type impurity in the lightly doped drain region;
forming side wall spacers overlying a portion of the gate structure;
performing a third implant process using a first impurity to form active source/drain regions in a vicinity of the surface region of the semiconductor substrate adjacent to the gate structure using the gate structure and the side wall spacers as a masking layer; and
performing a second thermal process to activate the first impurity in the active source/drain regions;
wherein the P type impurity is provided using a BF 2 precursor at an implant energy of 4.5 KeV to 10 KeV;
wherein the first thermal process is a spike anneal process provided at a temperature ranging from 650 degrees Celsius to 800 degrees Celsius,
wherein the second thermal process is a rapid thermal process provided at a temperature ranging from 700 degrees Celsius to 1000 degrees Celsius for a time period of 5 seconds to 10 seconds.
2. The method of claim 1 wherein the semiconductor substrate can be single crystal silicon, silicon germanium, or silicon on insulator (SOI).
3. The method of claim 1 wherein the P-type impurity is provided using a boron species.
4. The method of claim 1 wherein the precursor BF 2 is provided at a dose ranging from 1×10 13 to 1×10 15 atoms per cm 2 .
5. The method of claim 1 wherein the germanium species comprises germane provided at a dose ranging from 5×10 14 to 5×10 16 atoms per cm 2 and at an energy of 10 keV to 50 keV.
6. The method of claim 5 wherein the germanium species improves a sheet resistance characteristics of the lightly doped drain region.
7. The method of claim 1 wherein the second implant process includes co-implantation of at least a boron species and a carbon species.
8. The method of claim 7 wherein the carbon species is provided by a hydrocarbon.
9. The method of claim 7 wherein the carbon species reduce a transient enhanced diffusion resulting from the second implant process.
10. The method of claim 1 wherein the lightly doped drain region is characterized by a depth of 500 Angstroms and less.
11. The method of claim 1 wherein the first thermal process is performed in a time period of 20 seconds to 40 seconds.
12. The method of claim 1 wherein the first impurity comprises an N-type impurity.
13. The method of claim 1 wherein the first impurity comprises a P-type impurity.
14. The method of claim 1 wherein the third implant process is provided at an energy ranging from 10 keV to 50 keV at a dose ranging from 1×10 15 cm −2 to 5×10 16 cm −2 at a zero implant angle.