IP Library › Granted Patent US 8,384,231
Granted Patent B2
US 8,384,231 · App. 12/689,126 · Granted Feb 26, 2013

Method of forming a semiconductor die

Inventors: Gordon M. Grivna (Mesa, AZ); Michael J. Seddon (Gilbert, AZ)
Assignee: Semiconductor Components Industries, LLC
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Quick Facts
Patent No.
US 8,384,231
App. No.
12/689,126
Granted
Feb 26, 2013
Kind
B2
Abstract

In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer.

Claims (27)

1. A method of forming a semiconductor device comprising:

providing a first semiconductor die having a receptacle for receiving a second semiconductor die including using a dry etch method to sinqulate the first semiconductor die from a semiconductor wafer and to simultaneously form the receptacle;

positioning a second semiconductor die within the receptacle;

connecting the first semiconductor die to a first connection terminal, and connecting the second semiconductor die to a second connection terminal; and

encapsulating the first semiconductor die and the second semiconductor die within a semiconductor package.

2. The method of claim 1 wherein providing the first semiconductor die having the receptacle includes providing the first semiconductor die having the receptacle that is one of an opening through the first semiconductor die, a protrusion along a periphery of and extending outwardly from a side of the first semiconductor die, or a curved shape along the periphery of the first semiconductor die.

3. The method of claim 1 wherein positioning the second semiconductor die within the receptacle includes positioning the second semiconductor die that is formed on a substrate other than a silicon substrate.

4. The method of claim 1 wherein encapsulating the first semiconductor die and the second semiconductor die within the semiconductor package includes using a semiconductor package that includes one of a plastic body, a ceramic substrate, or a mold compound.

5. The method of claim 1 further including simultaneously singulating the first semiconductor die from a semiconductor wafer along with a plurality of semiconductor die.

6. A method of forming a semiconductor device comprising:

providing a first semiconductor die having a receptacle for receiving one of a component or a second semiconductor die including forming the receptacle while simultaneously using a dry etch for singulating the first semiconductor die from a semiconductor wafer;

positioning the component within the receptacle;

connecting the first semiconductor die to a first connection terminal;

connecting the component to one of the first semiconductor die or to a second connection terminal; and

encapsulating the first semiconductor die and the component.

7. The method of claim 6 wherein providing the first semiconductor die having the receptacle includes providing the first semiconductor die having the receptacle that is one of an opening through the first semiconductor die, a protrusion along a periphery of and extending outwardly from a side of the first semiconductor die, or a curved shape along the periphery of the first semiconductor die.

8. The method of claim 6 wherein positioning the component within the receptacle includes positioning one of a heat sink, an alignment key, a gallium arsenide active device, a non-silicon active device, a gallium nitride active device, or a passive electrical component.

9. The method of claim 6 further including forming the receptacle while singulatinq the first semiconductor die from a semiconductor wafer.

10. A semiconductor device comprising:

a first semiconductor die having a receptacle for receiving an electrical component wherein the receptacle is formed using a dry etch method to singulate the first semiconductor die from a semiconductor wafer and to simultaneously form the receptacle; and

a component positioned within the receptacle.

11. The semiconductor device of claim 10 wherein the receptacle includes one of an opening through the first semiconductor die, a protrusion along a periphery of and extending outwardly from a side of the first semiconductor die, or a curved shape along the periphery of the first semiconductor die.

12. The semiconductor device of claim 10 wherein the component is one of a second semiconductor die, a gallium arsenide active device, a non-semiconductor active device, a gallium nitride active device, a passive electrical component, a heat sink, an alignment pin, or a mold lock.

13. The semiconductor device of claim 10 further including encapsulating the semiconductor device.

14. The semiconductor die of claim 10 wherein the first semiconductor die has a multiply-connected topology.

15. The semiconductor die of claim 10 wherein the component is an electrical component.

16. The semiconductor die of claim 10 wherein the component is a mold lock.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2010
From: GRIVNA, GORDON M.; SEDDON, MICHAEL J.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 023803/0418 →
Continuity (1)
Related Publication 20110175242A1 · Jul 21, 2011