Systems and methods for implementing a programming sequence to enhance die interleave
Systems and methods for sequentially writing data to a memory device such as a universal serial bus (USB) memory device are disclosed. A system controller of a memory device including a first die and a second die, each of the first die and the second die including a plurality of pages, writes a first portion of a set of data to a lower page of a second die. The system controller then writes a second portion of the set of data to an upper page of the second die after writing the first portion of the set of data to the lower page of the second die.
1. A method for sequentially writing data to a memory device, the method comprising:
in a memory device comprising a first die and a second die, each of the first die and the second die comprising a plurality of pages:
receiving a first set of data;
writing the first set of data to one or more pages of the first die and the second die;
receiving a second set of data after writing the first set of data to the one or more pages of the first die and the second die;
writing a first portion of the second set of data to an upper page of the first die;
writing a second portion of the second set of data to a lower page of the second die after writing the first portion of the second set of data to the upper page of the first die;
writing a third portion of the second set of data to an upper page of the second die after writing the second portion of the second set of data to the lower page of the second die; and
writing a fourth portion of the second set of data to a lower page of the first die after writing the third portion of the second set of data to the upper page of the second die.
2. The method of claim 1 , wherein writing the fourth portion of the second set of data to the lower page of the first die after writing the third portion of the second set of data to the upper page of the second die comprises:
writing the fourth portion of the second set of data to the lower page of the first die approximately 320 μs after writing the third portion of the second set of data to the upper page of the second die.
3. The method of claim 1 , wherein writing the fourth portion of the second set of data to the lower page of the first die after writing the third portion of the second set of data to the upper page of the second die comprises:
writing the fourth portion of the second set of data to the lower page of the first die immediately after writing the third portion of the second set of data to the upper page of the second die.
4. The method of claim 1 , further comprising:
receiving a third set of data;
writing a first portion of the third set of data to a second upper page of the first die after writing the fourth portion of the second set of data to the lower page of the first die;
writing a second portion of the third set of data to a second lower page of the second die after writing the first portion of the third set of data to the second upper page of the first die;
writing a third portion of the third set of data to a second upper page of the second die after writing the second portion of the third set of data to the second lower page of the second die; and
writing a fourth portion of the third set of data to a second lower page of the first die after writing the third portion of the third set of data to the second upper page of the second die.
5. The method of claim 1 , wherein the first set of data is 64 Kilobytes of data and the second set of data is 64 Kilobytes of data.
6. The method of claim 1 , wherein writing the third portion of the second set of data to the upper page of the second die after writing the second portion of the second set of data to the lower page of the second die comprises:
writing the third portion of the second set of data to the upper page of the second die approximately 20 μs after writing the second portion of the second set of data to the lower page of the second die.
7. A memory device comprising:
a communication interface;
a memory unit comprising a first die and a second die, each of the first die and the second die comprising a plurality of pages; and
a processor for sequentially writing data received over the communication interface to one or more pages of the first die and the second die, the processor configured to:
receive a first set of data over the communication interface;
write the first set of data to the one or more pages of the first die and the second die;
receive a second set of data over the communication interface after writing the first set of data to the one or more pages of the first die and the second die;
write a first portion of the second set of data to an upper page of the first die;
write a second portion of the second set of data to a lower page of the second die after writing the first portion of the second set of data to the upper page of the first die;
write a third portion of the second set of data to an upper page of the second die after writing the second portion of the second set of data to the lower page of the second die; and
write a fourth portion of the second set of data to a lower page of the first die after writing the third portion of the second set of data to the upper page of the second die.
8. The memory device of claim 7 , wherein to write the fourth portion of the second set of data to the lower page of the first die after writing the third portion of the second set of data to the upper page of the second die, the processor is configured to:
write the fourth portion of the second set of data to the lower page of the first die approximately 320 μs after writing the third portion of the second set of data to the upper page of the second die.
9. The memory device of claim 7 , wherein to write the fourth portion of the second set of data to the lower page of the first die after writing the third portion of the second set of data to the upper page of the second die, the processor is configured to:
write the fourth portion of the second set of data to the lower page of the first die immediately after writing the third portion of the second set of data to the upper page of the second die.
10. The memory device of claim 7 , wherein the processor is further configured to:
receive a third set of data over the communication interface;
write a first portion of the third set of data to a second upper page of the first die after writing the fourth portion of the second set of data to the lower page of the first die;
write a second portion of the third set of data to a second lower page of the second die after writing the first portion of the third set of data to the second upper page of the first die;
write a third portion of the third set of data to a second an upper page of the second die after writing the second set portion of the third set of data to the second lower page of the second die; and
write a fourth portion of the third set of data to a second lower page of the first die after writing the third portion of the third set of data to the second upper page of the second die.
11. The memory device of claim 7 , wherein the first set of data is 64 Kilobytes of data and the second set of data is 64 Kilobytes of data.
12. The memory device of claim 7 , wherein to write the third portion of the second set of data to the upper page of the second die after writing the second portion of the second set of data to the lower page of the second die, the processor is configured to:
write the third portion of the second set of data to the upper page of the second die approximately 20 μs after writing the second portion of the second set of data to the lower page of the second die.