Global synchronization of parallel processors using clock pulse width modulation
A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.
1. A method for synchronizing a plurality of processors in a parallel computing system, the method comprising:
generating a clock signal;
performing a pulse width modification on the clock signal, the pulse width modification changing a pulse width within a clock period in the clock signal;
distributing the pulse width modified clock signal to a plurality of processors in the parallel computing system to synchronize the processors;
receiving, at one or more detection circuit associated with the processors, the distributed pulse width modified clock signal;
oversampling the received pulse width modified clock signal; and
generating a synchronization signal based on the oversampling, the generated synchronization signal used to synchronize the processors.
2. The method according to claim 1 , further comprising:
resetting the parallel computing system in response to the pulse width modified clock signal.
3. The method according to claim 1 , further comprising:
removing a jitter in the pulse width modified clock signal.
4. The method according to claim 1 , wherein the pulse width modification comprises one or more of:
removing a pulse within the clock period in the clock signal;
narrowing a pulse width within the clock period in the clock signal; and
widening a pulse width within the clock period in the clock signal.
5. The method according to claim 4 , wherein the narrowing includes a logical exclusive-OR operation.
6. The method according to claim 4 , wherein the widening includes a logical OR operation.
7. The method according to claim 4 , wherein the removing includes a logical exclusive OR operation.
8. The method according to claim 7 , further comprising:
detecting the pulse width modified clock signal.
9. The method according to claim 1 , wherein the oversampling comprises:
increasing a clock frequency of the pulse width modified clock signal.
10. The method according to claim 1 , wherein the synchronization signal interrupts the processors in the parallel computing system.
11. An apparatus for synchronizing a plurality of processors in a parallel computing system, the apparatus comprising:
a hardware module for generating a clock signal and for performing a pulse width modification on the clock signal, the pulse width modification changing a pulse width within a clock period in third clock signal;
a clock splitter for distributing the pulse width modified clock signal to a plurality of processors in the parallel computing system to synchronize the processors;
one or more detection circuit, associated with the processors, for receiving the pulse width modified clock signal;
a plurality of flip flops, in the one or more detection circuit, for oversampling the pulse width modified clock signal;
a hardware logic gate, in the one or more detection circuit, for generating a synchronization signal based on the oversampling, the generated synchronization signal used to synchronize the processors.
12. The apparatus according to claim 11 , further comprising:
a flip flop for removing a jitter in the pulse width modified clock signal.
13. The apparatus according to claim 11 , wherein the pulse width modification comprises one or more of:
removing a pulse within the clock period in the clock signal;
narrowing a pulse width within the clock period in the clock signal; and
widening a pulse width within the clock period in the clock signal.
14. The apparatus according to claim 13 , wherein a logical exclusive OR gate performs the narrowing.
15. The apparatus according to claim 13 , wherein a logical OR gate performs the widening.
16. The apparatus according to claim 13 , wherein a logical exclusive OR gate performs the removing.
17. The apparatus according to claim 11 , further comprising:
a phase locked loop or delay locked loop for increasing a clock frequency of the pulse width modified clock signal.
18. The apparatus according to claim 11 , wherein the hardware logic gate comprises a logical AND gate and a flip flop.
19. The apparatus according to claim 11 , wherein the synchronization signal interrupts the processors in the parallel computing system.
20. The apparatus according to claim 11 , further comprising:
a counter device for dividing a clock frequency of the generated clock signal.
21. A computer program product for synchronizing a plurality of processors in a parallel computing system, the computer program product comprising a non-transitory storage medium readable by a processing circuit and storing instructions run by the processing circuit for performing steps of:
generating a clock signal;
performing a pulse width modification on the clock signal, the pulse width modification changing a pulse width within a clock period in the clock signal;
distributing the pulse width modified clock signal to a plurality of processors in the parallel computing system to synchronize the processors;
receiving, at one or more detection circuit associated with the processors, the distributed pulse width modified clock signal;
oversampling the received pulse width modified clock signal; and
generating a synchronization signal based on the oversampling, the generated synchronization signal used to synchronize the processors.