Startup and protection circuitry for thin oxide output stage
A method for startup and operation of an output stage of a transmitter, the output stage comprising a first protection field effect transistor (FET) and a second protection FET includes enabling a startup circuit; providing a first bias voltage to the first protection FET in the output stage and a second bias voltage to the second protection FET stage in the output stage by the startup circuit; disabling the startup circuit and enabling a protection voltage generator; providing the first bias voltage to the first protection FET in the output stage by the protection voltage generator; and providing the second bias voltage to the second protection FET in the output stage by a second bias voltage power supply.
1. A method for startup and operation of an output stage of a transmitter, the output stage comprising a first protection field effect transistor (FET) and a second protection FET, the method comprising:
enabling a startup circuit;
providing a first bias voltage to the first protection FET in the output stage and a second bias voltage to the second protection FET in the output stage by the startup circuit;
disabling the startup circuit and enabling a protection voltage generator;
providing the first bias voltage to the first protection FET in the output stage by the protection voltage generator; and
providing the second bias voltage to the second protection FET in the output stage by a second bias voltage power supply;
wherein disabling the startup circuit and enabling the protection voltage generator comprises transitioning an enable signal from low to high, the enable signal being connected to both the startup circuit and the protection voltage generator, and further comprising differential clock connected to the protection voltage generator, wherein the differential clock is configured to turn on in the event the enable signal transitions from low to high.
2. The method of claim 1 , wherein the first protection FET comprises a protection FET for a pull-up branch of the output stage, the pull-up branch being connected between the first protection FET and a third voltage, and wherein the second protection FET comprises a protection FET for a pull-down branch of the output stage, the pull-down branch of the output stage being connected between the second protection FET and ground.
3. The method of claim 2 , wherein the first bias voltage received from the protection voltage generator is equal to the difference between the third voltage and the second bias voltage received from the power supply.
4. The method of claim 1 , wherein the enable signal is configured to transition from low to high in the event the second bias voltage power supply transitions from low to high.
5. The method of claim 1 , wherein the protection voltage generator comprises a capacitive voltage divider, the capacitive voltage divider comprising a first leg comprising a first p-type FET (pFET), a first capacitor, and a first n-type FET (nFET) in series, and a second leg comprising a second pFET, a second capacitor, and a second nFET in series, and wherein the differential clock alternately turns on the first leg while turning off the second leg, and then turns on the second leg while turning off the first leg, such that the first bias voltage is alternately provided to the output stage from the first leg and the second leg via a storage capacitor.
6. The method of claim 5 , wherein the first pFET and the second pFET comprise cross-coupled pFETs, and wherein the first nFET and the second nFET comprise cross-coupled nFET s.
7. The method of claim 1 , wherein the startup circuit comprises a self-biasing voltage divider.
8. The method of claim 1 , wherein the startup circuit further comprises a second bias voltage supply FET configured to connect the second bias voltage power supply to the output stage in the event the startup circuit is disabled.
9. A startup and protection system for an output stage of a transmitter, the output stage comprising a first protection field effect transistor (FET) and a second protection FET, the system comprising:
a startup circuit configured to provide a first bias voltage to the first protection FET and a second bias voltage to the second protection FET until the startup circuit is disabled;
a protection voltage generator configured to provide the first bias voltage to the first protection FET after the startup circuit is disabled;
a second bias voltage power supply configured to provide the second bias voltage to the second protection FET after the startup circuit is disabled;
an enable signal connected to both the startup circuit and the protection voltage generator, wherein the startup circuit is disabled when the enable signal transitions from low to high; and
a differential clock connected to the protection voltage generator, wherein the differential clock is configured to turn on in the event the enable signal transitions from low to high.
10. The system of claim 9 , wherein the first protection FET comprises a protection FET for a pull-up branch of the output stage, the pull-up branch being connected between the first protection FET and a third voltage, and wherein the second protection FET comprises a protection FET for a pull-down branch of the output stage, the pull-down branch of the output stage being connected between the second protection FET and ground.
11. The system of claim 10 , wherein the first bias voltage received from the protection voltage generator is equal to the difference between the third voltage and the second bias voltage received from the power supply.
12. The system of claim 9 , wherein the enable signal is configured to transition from low to high in the event the second bias voltage power supply transitions from low to high.
13. The system of claim 9 , wherein the protection voltage generator comprises a capacitive voltage divider, the capacitive voltage divider comprising a first leg comprising a first p-type FET (pFET), a first capacitor, and a first n-type FET (nFET) in series, and a second leg comprising a second pFET, a second capacitor, and a second nFET in series, and wherein the differential clock alternately turns on the first leg while turning off the second leg, and then turns on the second leg while turning off the first leg, such that the first bias voltage is alternately provided to the output stage from the first leg and the second leg via a storage capacitor.
14. The system of claim 13 , wherein the first pFET and the second pFET comprise cross-coupled pFETs, and wherein the first nFET and the second nFET comprise cross-coupled nFETs.
15. The system of claim 9 , wherein the startup circuit comprises a self-biasing voltage divider.
16. The system of claim 9 , wherein the startup circuit further comprises a second bias voltage supply FET configured to connect the second bias voltage power supply to the output stage in the event the startup circuit is disabled.