Self-aligned strap for embedded capacitor and replacement gate devices
After forming a planarization dielectric layer in a replacement gate integration scheme, disposable gate structures are removed and a stack of a gate dielectric layer and a gate electrode layer is formed within recessed gate regions. Each gate electrode structure is then recessed below a topmost surface of the gate dielectric layer. A dielectric metal oxide portion is formed above each gate electrode by planarization. The dielectric metal oxide portions and gate spacers are employed as a self-aligning etch mask in combination with a patterned photoresist to expose and metalize semiconductor surfaces of a source region and an inner electrode in each embedded memory cell structure. The metalized semiconductor portions form metal semiconductor alloy straps that provide a conductive path between the inner electrode of a capacitor and the source of an access transistor.
1. A semiconductor structure comprising:
a trench located in a semiconductor substrate;
a node dielectric located on a sidewall of said trench;
an inner electrode comprising a first doped semiconductor material and located within said node dielectric;
an access transistor located on said semiconductor substrate and including an access transistor source region comprising a second doped semiconductor material and contacting said node dielectric;
a metal semiconductor alloy portion contacting said inner electrode, said node dielectric, and said access transistor source region;
a field effect transistor different from said access transistor, located on said semiconductor substrate, and including another dielectric gate spacer, a source region, and a drain region, wherein said source region and said drain region are laterally surrounded by a shallow trench isolation structure; and
at least another metal semiconductor alloy portion located on said source region or said drain region and laterally spaced from at least one of said other dielectric gate spacer and said shallow trench isolation structure.
2. The semiconductor structure of claim 1 , wherein said access transistor comprises an access transistor gate structure that includes a gate dielectric, a gate conductor contacting said gate dielectric, a dielectric gate cap contacting a top surface of said gate conductor, and a dielectric gate spacer contacting outer sidewalls of said gate dielectric.
3. The semiconductor structure of claim 2 , wherein said gate dielectric contacts an entirety of inner sidewalls of said dielectric gate spacer.
4. The semiconductor structure of claim 2 , wherein outer sidewalls of said dielectric gate cap contacts an upper portion of inner sidewalls of said gate dielectric.
5. The semiconductor structure of claim 2 , wherein said dielectric gate cap comprises a dielectric metal oxide having a dielectric constant greater than 8.0.
6. The semiconductor structure of claim 1 , wherein said metal semiconductor alloy portion and said at least another metal semiconductor alloy portion include different metals.
7. The semiconductor structure of claim 1 , further comprising:
a planarization dielectric layer contacting at least one source region or at least one drain region of a field effect transistor; and
a contact level dielectric layer contacting a top surface of said planarization dielectric layer and said metal semiconductor alloy portion.
8. The semiconductor structure of claim 1 , further comprising a planarization dielectric layer in contact with sidewalls of said another dielectric gate spacer.
9. The semiconductor structure of claim 8 , wherein said planarization dielectric layer is not in contact with said metal semiconductor alloy portion.
10. The semiconductor structure of claim 8 , wherein a top surface of said planarization dielectric layer is coplanar with a top surface of said gate dielectric of said access transistor.
11. The semiconductor structure of claim 8 , further comprising a contact level dielectric layer contacting a top surface of said planarization dielectric layer.
12. The semiconductor structure of claim 11 , wherein said contact level dielectric layer is in contact with said metal semiconductor alloy portion.
13. The semiconductor structure of claim 12 , wherein an entirety of a top surface of said metal semiconductor alloy portion is in contact with said contact level dielectric layer.
14. The semiconductor structure of claim 11 , wherein said contact level dielectric layer is not in contact with said at least another metal semiconductor alloy portion.
15. The semiconductor structure of claim 11 , wherein a bottom surface of said contact level dielectric layer is in contact with a top surface of a gate dielectric of said access transistor.
16. The semiconductor structure of claim 15 , wherein a top surface of one of said at least another metal semiconductor alloy portion has a same horizontal cross-sectional area as a bottom surface of said contact via structure.
17. The semiconductor structure of claim 1 , further comprising:
a contact level dielectric layer overlying said metal semiconductor alloy portion and said at least one metal semiconductor alloy portion; and
a contact via structure embedded in at least said contact level dielectric layer.
18. The semiconductor structure of claim 1 , further comprising a contact level dielectric layer in contact with said metal semiconductor alloy portion and said at least another metal semiconductor alloy portion.
19. The semiconductor structure of claim 18 , wherein said gate dielectric of said access transistor laterally surround a dielectric gate cap of said access transistor that overlies said gate conductor of said access transistor.
20. The semiconductor structure of claim 1 , wherein a gate dielectric of said access transistor laterally surrounds a gate conductor of said access transistor.