IP Library Granted Patent US 8,530,921
Granted Patent B2
US 8,530,921 · App. 13/190,126 · Granted Sep 10, 2013

High voltage low current surface emitting LED

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Quick Facts
Patent No.
US 8,530,921
App. No.
13/190,126
Granted
Sep 10, 2013
Kind
B2
Abstract

A monolithic LED chip is disclosed comprising a plurality of junctions or sub-LEDs (“sub-LEDs”) mounted on a submount. The sub-LEDs are serially interconnected such that the voltage necessary to drive the sub-LEDs is dependent on the number of serially interconnected sub-LEDs and the junction voltage of the sub-LEDs. Methods for fabricating a monolithic LED chip are also disclosed with one method comprising providing a single junction LED on a submount and separating the single junction LED into a plurality of sub-LEDs. The sub-LEDs are then serially interconnected such that the voltage necessary to drive the sub-LEDs is dependent on the number of the serially interconnected sub-LEDs and the junction voltage of the sub-LEDs.

Claims (24)

1. A monolithic LED chip, comprising a plurality of serially-interconnected sub-LEDs bonded to a submount by a common bond layer that is not electrically connected to the sub-LEDs.

2. The LED chip of claim 1 , further comprising electrically conductive features that are disposed on a side of the common bond layer opposite the submount and that serially interconnect said sub-LEDs.

3. The LED chip of claim 2 , wherein said electrically conductive features comprise bottom contacts and connector traces.

4. The LED chip of claim 2 , wherein said electrically conductive features comprise wire bond pads.

5. The LED chip of claim 2 , further comprising electrically insulating features that insulate said electrically conductive features from other portions of said LED chip to prevent shorting of signals on said electrically conductive features.

6. The LED chip of claim 1 , wherein the alignment tolerance between said sub-LEDs is less than 5 microns.

7. The LED chip of claim 1 , wherein the alignment tolerance between said sub-LEDs is less than 2 microns.

8. The LED chip of claim 1 , wherein said sub-LEDs are formed from a single junction LED.

9. The LED chip of claim 8 , wherein said sub-LEDs are formed from a single junction LED by removing portions of said single junction LED.

10. The LED chip of claim 8 , wherein said sub-LEDs are formed from a single junction LED by isolation implants.

11. The LED chip of claim 8 , wherein the active area utilization ratio is greater than 50%.

12. The LED chip of claim 8 , wherein the active area utilization ratio is greater than 75%.

13. The LED chip of claim 1 , further comprising an insulating layer between said sub-LEDs and substrate.

14. The LED chip of claim 1 , further comprising an insulator layer between said sub-LEDs and said submount.

15. The LED chip of claim 14 , wherein said insulator layer has a thickness to tolerate the voltage driving said sub-LEDs.

16. The LED chip of claim 1 , emitting a white light from said sub-LEDs.

17. The LED chip of claim 1 , emitting down converted light from said sub-LEDs.

18. The LED chip of claim 1 , wherein the remaining ones of said serially connected sub-LEDs are capable of emitting light in response to said drive voltage when one of said sub-LEDs fail.

19. The LED chip of claim 2 , wherein the electrically conductive features comprise at least one conductive trace contacting a top surface of a bottom contact of a first one of the sub-LEDs and a top surface of a second one of the sub-LEDs.

20. The LED chip of claim 19 , wherein the at least one conductive trace has a portion that conforms to a side surface of the second one of the sub-LEDs.

21. The LED chip of claim 20 , further comprising at least one insulating layer insulating the side surface from the at least one conductive trace.

22. The LED chip of claim 21 , wherein the at least one insulating layer fills a gap between bottom contacts of the first and second ones of the sub-LEDs.

23. The LED chip of claim 19 , further comprising at least one insulating layer insulating at least one of the first and second ones of the sub-LEDs from the at least one conductive trace.

24. The LED chip of claim 23 , wherein the at least one insulating layer fills a gap between bottom contacts of the first and second ones of the sub-LEDs.

Assignments (5)
PATENT SECURITY AGREEMENT Recorded Jun 30, 2025
From: CREELED, INC.; PENGUIN SOLUTIONS CORPORATION (DE); SMART EMBEDDED COMPUTING, INC.; SMART HIGH RELIABILITY SOLUTIONS LLC; SMART MODULAR TECHNOLOGIES, INC.; PENGUIN COMPUTING, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 071755/0001 →
RELEASE OF PATENT SECURITY INTEREST RECORDED AT R/F 058983/0001 Recorded Jun 25, 2025
From: CITIZENS BANK, N.A.
To: SMART MODULAR TECHNOLOGIES, INC.; SMART EMBEDDED COMPUTING, INC.; SMART HIGH RELIABILITY SOLUTIONS LLC; CREELED, INC.
Reel/Frame 071725/0207 →
SECURITY INTEREST Recorded Feb 7, 2022
From: SMART MODULAR TECHNOLOGIES, INC.; SMART HIGH RELIABILITY SOLUTIONS, LLC; SMART EMBEDDED COMPUTING, INC.; CREELED, INC.
To: CITIZENS BANK, N.A.
Reel/Frame 058983/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2021
From: CREE, INC.
To: CREELED, INC.
Reel/Frame 057017/0311 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2021
From: IBBETSON, JAMES; HEIKMAN, STEN
To: CREE, INC.
Reel/Frame 056870/0436 →