IP Library Granted Patent US 8,552,747
Granted Patent B2
US 8,552,747 · App. 12/976,182 · Granted Oct 8, 2013

Capacitance discrimination circuit and touch switch equipped with the same

Inventor: Susumu Yamada (Oizumi-machi, JP)
Assignee: Semiconductor Components Industries, LLC
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,552,747
App. No.
12/976,182
Granted
Oct 8, 2013
Kind
B2
Abstract

In some embodiments, a capacitance discrimination circuit includes first and second capacitors, a comparator configured to compare a first voltage of the first capacitor and a second voltage of the second capacitor, a counter circuit configured to perform a count operation based on a comparison result of the comparator, a charge circuit configured to charge the first and second capacitors, and a control circuit configured to control the charge circuit so as to charge either the first capacitor or the second capacitor based on the comparison result of the comparator. The capacitance discrimination of the first and second capacitors is performed based on count values of the counter circuit. The capacitance discrimination circuit preferably includes a discharge circuit to discharge electric charges stored in the first and second capacitors in accordance with a discharge signal from the control circuit.

Claims (49)

1. A capacitance discrimination circuit comprising:

a first capacitor;

a second capacitor;

a comparator configured to compare a first voltage of the first capacitor and a second voltage of the second capacitor;

a counter circuit configured to perform a count operation based on a comparison result of the comparator;

a charge circuit configured to charge the first capacitor and the second capacitor; and

a control circuit configured to control the charge circuit so as to charge one of the first capacitor and the second capacitor lower in voltage based on a comparison result of the comparator,

wherein capacitance discrimination of the first capacitor and the second capacitor is performed based on count values of the counter circuit.

2. A capacitance discrimination circuit comprising:

a first capacitor;

a second capacitor;

a comparator configured to compare a first voltage of the first capacitor and a second voltage of the second capacitor;

a counter circuit configured to perform a count operation based on a comparison result of the comparator;

a charge circuit configured to charge the first capacitor and the second capacitor; and

a control circuit configured to control the charge circuit so as to charge either the first capacitor or the second capacitor based on a comparison result of the comparator, wherein capacitance discrimination of the first capacitor and the second capacitor is performed based on count values of the counter circuit;

wherein the counter circuit includes:

a first counter configured to perform a count operation when the comparison result of the comparator is a first value;

a second counter configured to perform a count operation when the comparison result of the comparator is not the first value; and

a third counter configured to count a predetermined time period,

wherein, when it is discriminated by the third counter that the predetermined time period has passed, the capacitance discrimination of the first capacitor and the second capacitor is performed based on the count values of the first counter and the second counter.

3. The capacitance discrimination circuit as recited in claim 2 , further comprising a discharge circuit configured to discharge electric charges stored in the first capacitor and the second capacitor, wherein the discharge circuit causes discharging of the electric charges stored in the first capacitor and the second capacitor in accordance with a discharge signal from the control circuit.

4. The capacitance discrimination circuit as recited in claim 2 , wherein the first counter is configured to perform a count-up operation when it is discriminated by the comparator that the first capacitor is lower in voltage than the second capacitor, and wherein the second counter is configured to perform a count-up operation when it is discriminated by the comparator that the second capacitor is lower in voltage than the first capacitor.

5. The capacitance discrimination circuit as recited in claim 1 ,

further comprising a discharge circuit configured to discharge electric charges stored in the first capacitor and the second capacitor, wherein the discharge circuit causes discharging of the electric charges stored in the first capacitor and the second capacitor in accordance with a discharge signal from the control circuit.

6. The capacitance discrimination circuit as recited in claim 1 , wherein the counter is an up/down counter configured to perform a count-up operation when it is discriminated by the comparator that the first capacitor is lower in voltage than the second capacitor and a count-down operation when it is discriminated by the comparator that the second capacitor is lower in voltage than the first capacitor.

7. The capacitance discrimination circuit as recited in claim 1 , wherein the capacitance discrimination circuit is built-in an LSI circuit.

8. The capacitance discrimination circuit as recited in claim 1 , wherein:

the capacitance discrimination circuit includes N pieces of capacitors including the first and second capacitors;

the comparator is configured to compare voltages of the N pieces of capacitors;

the counter circuit has counters corresponding to each of the N pieces of capacitors and configured to perform a count operation based on a comparison result of the comparator;

the charge circuit is configured to charge the N pieces of capacitors;

the control circuit is configured to control the charge circuit so as to charge one of the capacitors lowest in voltage among the N pieces of capacitors based on the comparison result of the comparator; and

capacitance discrimination of the N pieces of capacitors is performed based on count values of the counter circuit.

9. The capacitance discrimination circuit as recited in claim 8 , further comprising a discharge circuit configured to discharge electric charges stored in the N pieces of capacitors, wherein the discharge circuit causes discharging of the electric charges stored in the N pieces of capacitors in accordance with a discharge signal from the control circuit.

10. A touch switch equipped with the capacitance discrimination circuit as cited in claim 1 , wherein the touch switch is configured to discriminate whether or not a finger of a user is being touched based on the discrimination result of the capacitance discrimination circuit.

11. The touch switch as recited in claim 10 , wherein the counter circuit includes:

a first counter configured to perform a count operation when the comparison result of the comparator is a first value;

a second counter configured to perform a count operation when the comparison result of the comparator is not the first value; and

a third counter configured to count a predetermined time period,

wherein, when it is discriminated by the third counter that the predetermined time period has passed, the capacitance discrimination of the first capacitor and the second capacitor is performed based on the count values of the first counter and the second counter.

12. The touch switch as recited in claim 10 , further comprising a discharge circuit configured to discharge electric charges stored in the first capacitor and the second capacitor, wherein the discharge circuit causes discharging of the electric charges stored in the first capacitor and the second capacitor in accordance with a discharge signal from the control circuit.

13. The touch switch as recited in claim 10 , wherein the first counter is configured to perform a count-up operation when it is discriminated by the comparator that the first capacitor is lower in voltage than the second capacitor, and wherein the second counter is configured to perform a count-up operation when it is discriminated by the comparator that the second capacitor is lower in voltage than the first capacitor.

14. The touch switch as recited in claim 10 , wherein the counter is an up/down counter configured to perform a count-up operation when it is discriminated by the comparator that the first capacitor is lower in voltage than the second capacitor and a count-down operation when it is discriminated by the comparator that the second capacitor is lower in voltage than the first capacitor.

15. A capacitance discrimination method of discriminating capacitance of a plurality of capacitors, the method comprising the steps of:

comparing voltages of the plurality of capacitors;

performing a count operation on one of the plurality of capacitors lowest in voltage based on a comparison result of the voltages of the plurality of capacitors to obtain a count value on each of the plurality of capacitors;

charging one of the plurality of capacitors lowest in voltage based on the comparison result of the voltages of the plurality of capacitors; and

discriminating capacitance of the plurality of capacitors based on the count values of the count operation.

16. The capacitance discrimination method of discriminating capacitance of a plurality of capacitors as recited in claim 15 , further comprising a step of discharging electric charges stored in the plurality of capacitors prior to the step of comparing the voltages of the plurality of capacitors.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2013
From: SANYO SEMICONDUCTOR CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 031729/0866 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 23, 2010
From: YAMADA, SUSUMU
To: SANYO ELECTRIC CO., LTD.; SANYO SEMICONDUCTOR CO., LTD.
Reel/Frame 025568/0006 →
Priority Claims (1)
JP 2009-290567 · Dec 22, 2009 · national
Continuity (1)
Related Publication 20110148439A1 · Jun 23, 2011