Low-power class D amplifier using multistate analog feedback loops
An audio amplifier system may include an audio CODEC/output (AOP) path featuring analog class-D amplifiers, and using Natural Sampling Pulse Width Modulation (PWM) to convert an analog input into a series of Rail-to-Rail pulses. The audio signal may be encoded in the average value of the PWM pulse train and may be recovered from the PWM signal by analog low pass filtering. The Class-D amplifiers may be designed with a negative feedback loop/network to compare the output signal with the input signal and suppress non-idealities introduced by the Class-D switching stage. Furthermore, operation of the AOP may be designed according to a separate signal transfer function and a separate noise transfer function, and 2 nd order noise shaping may be performed at low power, with an optimized filter included in the feedback loop to achieve the best noise reduction at low power. Operation of the amplifier feedback network may be similar to that of a continuous time, low-pass delta-sigma modulator, but with a PWM loop wrapped around the class-D power amplifier.
1. An audio processing system comprising:
a dynamic element matching (DEM) component having an output comprising a first number of bits, and further having an input comprising a second number of bits configured to receive a digital audio signal in a first format, wherein the DEM component is configured to:
convert the digital audio signal into a second format;
while converting the digital audio signal into the second format, randomize an ordering of the output bits of the DEM component with respect to the input bits of the DEM component; and
provide the converted digital audio signal through the output bits of the DEM component according to the randomized ordering of the output bits of the DEM component;
a digital-to-analog converter (DAC) having an input comprising a first number of bits configured to receive the converted digital audio signal from the DEM component, wherein the DAC is configured to convert the converted digital audio signal into a corresponding analog signal; and
an amplifier network having an input configured to receive the analog signal and generate a modulated digital signal based on the analog signal, wherein the amplifier network comprises a negative feedback loop between an output of the amplifier network and the input of the amplifier network, implementing a transfer function configured to reconstruct the analog signal from the modulated digital signal while attenuating quantization noise to produce an amplified driving signal at the output of the amplifier network.
2. The audio processing system of claim 1 , wherein the negative feedback loop is a Pulse Width Modulation loop.
3. The audio processing system of claim 1 , wherein the amplifier network comprises:
a first integrator configured to produce a first integrated signal based on a difference of the analog input signal and a filtered version of the amplified driving signal; and
a second integrator configured to produce a second integrated signal based on a sum of the first integrated signal and the filtered version of the amplified driving signal;
wherein the amplifier network is configured to generate the modulated digital signal based on the second integrated signal.
4. The audio processing system of claim 3 , wherein the amplifier network further comprises a Triangle Wave Generator (TWG) configured to generate a high-speed triangle wave signal; and
a comparator configured to compare the second integrated signal to the triangle wave signal to encode the analog signal into a naturally sampled PWM signal which is the modulated digital signal;
wherein the amplifier network is configured to generate the amplified driving signal based on the PWM signal.
5. The audio processing system of claim 4 , wherein the second integrator is configured with a passive pole at its output to attenuate noise near a clock frequency of the PWM signal.
6. The audio processing system of claim 4 , wherein the amplifier network further comprises a class-D amplifier configured to receive the PWM signal and generate the amplified driving signal from the PWM signal.
7. The audio processing system of claim 4 , wherein the PWM signal comprises a pair of non-overlapping signals, wherein the amplifier network further comprises timing logic configured to delay edge transitions of the non-overlapping signals to avoid shoot-through current produced during switching of the PWM signal.
8. The audio processing system of claim 4 , wherein an output fundamental of the TWG is one half that of a specified input frequency of a clock signal used for clocking the TWG, to set a natural sampling frequency of the PWM signal.
9. The audio processing system of claim 4 , wherein the amplifier network further comprises a feedback filter coupled between the output of the amplifier network and an input of the first integrator, and between the output of the amplifier network and an input of the second integrator.
10. The system of claim 4 , wherein the amplifier network further comprises a feedback filter coupled between the output of the amplifier network and an input of the first integrator, and between the output of the amplifier network and an input of the second integrator;
wherein the first integrator is configured to produce the first integrated signal based on the analog input signal and a filtered version of the amplified driving signal, and wherein the second integrator is configured to produce the second integrated signal based on the first integrated signal and the filtered version of the amplified driving signal.
11. A method for reducing noise at low power operation of a class-D amplifier amplifying an audio signal, the method comprising:
receiving a digital audio signal in a first format at an input of a dynamic element matching (DEM) component, wherein the DEM component has an output comprising a first number of bits, and wherein the input of the DEM comprises a second number of bits;
the DEM component converting the digital audio signal into a second format, comprising randomizing an ordering of the output bits of the DEM component with respect to the input bits of the DEM component;
the DEM component providing the converted digital audio signal through the output bits of the DEM component according to the randomized ordering of the output bits of the DEM component;
receiving the converted digital audio signal at the input of a digital-to-analog converter (DAC), wherein the input of the DAC comprises a first number of bits;
the DAC converting the converted digital audio signal into a corresponding analog signal;
generating a modulated digital signal based on the analog signal;
producing an amplified driving signal by reconstructing the analog signal from the modulated digital signal and attenuating quantization noise.
12. The method of claim 11 , wherein said generating and said producing are performed in a negative feedback loop configured to compare the analog signal and the amplified driving signal to suppress non-idealities introduced during said reconstructing.
13. The method of claim 11 , further comprising:
producing a first integrated signal based on a difference of the analog input signal and a filtered version of the amplified driving signal; and
producing a second integrated signal based on a sum of the first integrated signal and the filtered version of the amplified driving signal;
wherein said generating comprises generating the modulated digital signal from the second integrated signal.
14. The method of claim 13 , wherein said generating the modulated digital signal comprises:
generating a high-speed triangle wave signal; and
encoding the analog signal into a naturally sampled PWM signal by comparing the second integrated signal to the triangle wave signal; and
providing the PWM signal as the modulated digital signal.
15. The method of claim 14 , further comprising:
receiving the PWM signal at an input of a class-D amplifier; and
the class-D amplifier generating the amplified driving signal from the PWM signal.
16. The method of claim 14 , wherein said providing the PWM signal comprises providing a pair of non-overlapping signals, comprising delaying edge transitions of the non-overlapping signals to avoid shoot-through current produced during switching of the PWM signal.
17. A system comprising:
an audio source configured to generate a digital audio signal in a first format having a resolution of a first number of bits; and
an audio path comprising:
a dynamic element matching (DEM) component configured to:
receive the digital audio signal and convert the digital audio signal into a second format having a resolution of a second number of bits;
randomize an ordering of output bits of the DEM component with respect to input bits of the DEM component; and
provide the converted digital audio signal through the output bits of the DEM component according to the randomized ordering of the output bits of the DEM component;
a digital-to-analog converter (DAC) configured to receive the converted digital audio signal, and further configured to convert the converted digital audio signal into a corresponding analog signal; and
an amplifier network configured to receive the analog signal at an input of the amplifier network, and further configured to generate a modulated digital signal based on the analog signal, wherein the amplifier network comprises a negative feedback loop between an output of the amplifier network and the input of the amplifier network to reconstruct the analog signal from the modulated digital signal while attenuating quantization noise, to produce an amplified driving signal at the output of the amplifier network.
18. The system of claim 17 , wherein the negative feedback loop is a Pulse Width Modulation loop.
19. The system of claim 17 , wherein the amplifier network comprises:
a first integrator configured to produce a first integrated signal based on the analog input signal and the amplified driving signal; and
a second integrator configured to produce a second integrated signal based on the first integrated signal and the amplified driving signal;
wherein the amplifier network is configured to generate the modulated digital signal based on the second integrated signal.
20. The system of claim 19 , wherein the amplifier network further comprises a Triangle Wave Generator (TWG) configured to generate a high-speed triangle wave signal; and
a comparator configured to compare the second integrated signal to the triangle wave signal to produce a PWM signal as the modulated digital signal.
21. The system of claim 20 , wherein the second integrator is configured with a passive pole at its output to attenuate noise near a clock frequency of the PWM signal.
22. The audio processing system of claim 20 , wherein the amplifier network further comprises a class-D amplifier configured to receive the PWM signal and generate the amplified driving signal from the PWM signal.
23. The audio system of claim 20 , wherein the PWM signal comprises a pair of non-overlapping signals, wherein the amplifier network further comprises timing logic configured to delay edge transitions of the non-overlapping signals to avoid shoot-through current produced during switching of the PWM signal.
24. The system of claim 20 , wherein an output fundamental of the TWG is one half of a fundamental of a specified input frequency of a clock signal used for clocking the TWG, to set a natural sampling frequency of the PWM signal.
25. The system of claim 17 , further comprising a load coupled to the output of the amplifier network to be driven by the amplified driving signal.
26. The system of claim 25 , wherein the load is a pair of stereo headphones.