Granted Patent B1

US 8,554,815 · App. 12/621,361 · Granted Oct 8, 2013

Inventors: Viet Linh Do (Carlsbad, CA); Simon Pang (San Diego, CA)

Assignee: Applied Micro Circuits Corporation

Abstract

Claims (743)

1. In a frequency synthesis device, a method for synthesizing signal frequencies using a single reference clock and a primitive ratio of integers, the method comprising:

accessing a plurality (k) of reference clock frequency values (f r i ), where 1≦i≦k, and also accessing a plurality of synthesized clock frequency values (f o i );

for each synthesized clock frequency value, calculating a raw ratio of integers Np raw i and Dp raw i , such that:

f

o

i

=

Np

raw

i

Dp

raw

i

×

f

r

i

;

finding a greatest common divisor (GCD) of Np raw i and Dp raw i (GCD(Np raw i ,Dp raw i )), and primitive ratio of integers Np i and

Dp

i

⁡

(

Np

i

Dp

i

)

,

for each raw ratio of integers, such that:

N

p

i

=

Np

raw

i

GCD

⁡

(

Np

raw

i

,

Dp

raw

i

)

;

and

D

p

i

=

Dp

raw

i

GCD

⁡

(

Np

raw

i

,

Dp

raw

i

)

;

selecting a common clock frequency value (f cr );

performing a calculation to determine a final ratio of integers N cr i and D cr i

(

C

·

(

N

cr

i

D

cr

i

)

)

for each synthesized clock frequency value, the calculation a function of values selected from the common clock frequency value, each primitive ratio of integers, each reference clock frequency value, where C is an integer value;

storing each final ratio of integers, cross-referenced to its associated synthesized clock frequency value, in a tangible memory medium; and

using a final ratio of integers accessed from the tangible memory medium to generate the associated synthesized clock frequency value.

2. The method of claim 1 further comprising:

receiving a command to generate synthesized clock frequencies f o i ;

accessing the memory to recover the final ratio of integers N cr i and D cr i ,

C

·

(

N

cr

i

D

cr

i

)

,

associated with f o i ;

supplying the final ratio of integers to a flexible accumulation module;

creating a divisor; and,

using the divisor and a common clock signal having a frequency equal to the common clock value to generate a synthesized signal having a frequency equal to the synthesized frequency value.

3. The method of claim 1 wherein the calculation includes finding:

N

cr

i

=

f

r

i

×

N

p

i

GCD

⁡

(

f

r

i

,

f

cr

)

×

GCD

⁡

(

f

r

i

×

N

p

i

GCD

⁡

(

f

r

i

,

f

cr

)

,

f

r

i

×

D

p

i

GCD

⁡

(

f

r

i

,

f

cr

)

)

;

and

,

⁢

D

cr

i

=

f

cr

×

D

p

i

GCD

⁡

(

f

r

i

,

f

cr

)

×

GCD

⁡

(

f

r

i

×

N

p

i

GCD

⁡

(

f

r

i

,

f

cr

)

,

f

r

i

×

D

p

i

GCD

⁡

(

f

r

i

,

f

cr

)

)

,

⁢

when

⁢

⁢

f

cr

≠

f

r

i

.

4. The method of claim 1 wherein the calculation includes finding:

N

cr

i

=

N

p

i

GCD

⁡

(

N

p

i

,

D

p

i

)

;

D

cr

i

=

D

p

i

GCD

⁡

(

N

p

i

,

D

p

i

)

⁢

⁢

when

⁢

⁢

f

cr

=

f

r

i

.

5. The method of claim 2 wherein supplying the final ratio to the flexible accumulator module includes reducing the ratio

C

·

N

cr

i

D

cr

i

to an integer and ratio

P

⁡

(

n

cr

i

d

cr

i

)

,

where

n

cr

i

d

cr

i

is <1 (decimal); and,

wherein generating the divisor includes summing P with a k-bit quotient.

6. The method of claim 5 wherein reducing the ratio

N

cr

i

D

cr

i

to an integer and ratio

P

⁡

(

n

cr

i

d

cr

i

)

includes supplying

n

cr

i

d

cr

i

to the flexible accumulator module with a plurality of series-connected flexible accumulators; and,

the method further comprising:

generating the k-bit quotient as follows:

generating a binary sequence from each flexible accumulator; and,

using a plurality of binary sequences to generate the k-bit quotient.

7. The method of claim 5 wherein supplying

n

cr

i

d

cr

i

to the flexible accumulator module includes supplying an r-bit binary numerator and an (r+1)-bit binary denominator.

8. The method of claim 1 wherein calculating the final ratio of integers N cr i and D cr i ,

C

·

(

N

cr

i

D

cr

i

)

,

for each synthesized clock frequency value includes calculating

E

·

(

(

F

)

⁢

N

cr

i

(

F

)

⁢

D

cr

i

)

for each synthesized clock frequency, where (E)(F)=C.

9. In a frequency synthesis device, a system for synthesizing signal frequencies using a single reference clock and a primitive ratio of integers, the system comprising:

a calculator configured to accept a plurality (k) of reference clock frequency values (f r i ), where 1≦i≦k, and to accept a plurality of synthesized clock frequency values (f o i ), the calculator calculating a raw ratio of integers Np raw i and Dp raw i for each synthesized clock frequency value, such that:

f

o

i

=

Np

raw

i

Dp

raw

i

×

f

r

i

;

a common reference ratio (CRR) module having an input to accept a common clock frequency value (f cr ) and the raw ratio of integers from the calculator, the CRR module finding a greatest common divisor (GCD) of Np raw i and Dp raw i ,

(GCD (Np raw i ,Dp raw i )), and primitive ratio of integers Np i and

Dp

i

⁡

(

Np

i

Dp

i

)

,

for each raw ratio of integers, such that:

N

p

i

=

Np

raw

i

GCD

⁡

(

Np

raw

i

,

Dp

raw

i

)

;

and

D

p

i

=

Dp

raw

i

GCD

⁡

(

Np

raw

i

,

Dp

raw

i

)

;

the CRR module performing a calculation of a final ratio of integers N cr i and

D

cr

i

⁡

(

C

·

(

N

cr

i

D

cr

i

)

)

for each synthesized clock frequency value at an output, the calculation a function of values selected from the common clock frequency value, each primitive ratio of integers, each reference frequency value, and each GCD, where C is an integer value; and,

a memory including a table for storing the final ratio of integers from the CRR module, where each final ratio of integers is cross-referenced to its associated synthesized clock frequency value, wherein a final ratio of integers accessed from the table in the memory is used to generate the associated synthesized clock frequency value.

10. The system of claim 9 wherein the memory has an input to accept a command to generate synthesized clock frequencies f o i ;

the system further comprising:

a flexible accumulator having an interface operable for accessing the table in memory, in response to the command to generate the synthesized clock frequencies f o i , to recover the final ratio of integers

C

·

(

N

cr

i

D

cr

i

)

associated with f o i , and further operable for creating a divisor; and,

a clock synthesis unit (CSU) having inputs to accept the divisor and a common clock signal having a frequency equal to the common clock value, and an output to supply a synthesized signal having a frequency equal to the synthesized frequency value.

11. The system of claim 9 wherein the calculation includes finding:

N

cr

i

=

f

r

i

×

N

p

i

GCD

⁡

(

f

r

i

,

f

cr

)

×

GCD

⁡

(

f

r

i

×

N

p

i

GCD

⁡

(

f

r

i

,

f

cr

)

,

f

cr

×

D

p

i

GCD

⁡

(

f

r

i

,

f

cr

)

)

;

and

,

⁢

D

cr

i

=

f

cr

×

D

p

i

GCD

⁡

(

f

r

i

,

f

cr

)

×

GCD

⁡

(

f

r

i

×

N

p

i

GCD

⁡

(

f

r

i

,

f

cr

)

,

f

cr

×

D

p

i

GCD

⁡

(

f

r

i

,

f

cr

)

)

,

⁢

when

⁢

⁢

f

cr

≠

f

r

i

.

12. The system of claim 9 wherein the calculation includes finding:

N

cr

i

=

N

p

i

GCD

⁡

(

N

p

i

,

D

p

i

)

;

and

,

⁢

D

cr

i

=

D

p

i

GCD

⁡

(

N

p

i

,

D

p

i

)

⁢

⁢

when

⁢

⁢

f

cr

=

f

r

i

.

13. The system of claim 10 wherein the CRR module reduces the ratio C·

N

cr

i

D

cr

i

to an integer and ratio

P

⁡

(

n

cr

i

d

cr

i

)

,

where

n

cr

i

d

cr

i

is <1 (decimal); and

wherein the flexible accumulator module generates a divisor by summing P with a k-bit quotient.

14. The system of claim 13 wherein the flexible accumulator module includes a plurality of series-connected flexible accumulators, where each flexible accumulator generates a binary sequence, and a plurality of binary sequences are used to generate the k-bit quotient.

15. The system of claim 13 wherein the flexible accumulator module accesses

C

·

n

cr

i

d

cr

i

from the table in memory, where n cr is an r-bit binary numerator and d cr is an (r+1)-bit binary denominator.

16. The system of claim 9 wherein the CRR module calculates

E

·

(

(

F

)

⁢

N

cr

i

(

F

)

⁢

D

cr

i

)

for each synthesized clock frequency, where (E)(F)=C.

Assignments (3)

Continuity (9)