Off-line gain calibration in a time-interleaved analog-to-digital converter
A time-interleaved analog-to-digital converter (ADC) includes a plurality of ADC blocks each including: at least one ADC unit configured to convert an analog input to a digital output; and a digital gain controller configured to adjust a reference voltage of the at least one ADC unit based on a comparison of an actual output of the at least one ADC unit to an expected output of the at least one ADC unit.
1. A time-interleaved analog-to-digital converter (ADC), comprising:
a plurality of ADC blocks each comprising:
at least one ADC unit configured to convert an analog input to a digital output; and
a digital gain controller configured to adjust a reference voltage of the at least one ADC unit based on a comparison of an actual output of the at least one ADC unit to an expected output of the at least one ADC unit.
2. The time-interleaved ADC of claim 1 , further comprising an interleaver circuit and a digital-to-analog converter (DAC), wherein:
the interleaver circuit provides an initial reference voltage to the DAC; and
the DAC generates the reference voltage of the at least one ADC unit by adjusting the initial reference voltage.
3. The time-interleaved ADC of claim 2 , wherein the DAC adjusts the initial reference voltage based on at least one control signal from the digital gain controller.
4. The time-interleaved ADC of claim 2 , wherein:
the DAC comprises a resistor string; and
the DAC adjusts the initial reference voltage by changing a tap location along the resistor string.
5. The time-interleaved ADC of claim 2 , further comprising a voltage regulator between the DAC and the at least one ADC unit, wherein the voltage regulator regulates the reference voltage of the at least one ADC unit.
6. The time-interleaved ADC of claim 2 , wherein the interleaver circuit provides samples of a reference waveform to the at least one ADC unit.
7. The time-interleaved ADC of claim 6 , wherein the expected output of the at least one ADC unit is based on the reference waveform.
8. The time-interleaved ADC of claim 6 , wherein:
the reference waveform has an amplitude that is less than a full scale of the at least one ADC unit; and
the reference waveform is one of a square wave and a pseudo random binary signal (PRBS).
9. The time-interleaved ADC of claim 2 , wherein the initial reference voltage is greater than a nominal full scale reference voltage of the at least one ADC unit.
10. The time-interleaved ADC of claim 1 , wherein:
the digital gain controller calculates a first average of first digital outputs of the at least one ADC unit;
the digital gain controller calculates a second average of second digital outputs of the at least one ADC unit; and
the actual output is a difference between the first average and the second average.
11. The time-interleaved ADC of claim 1 , wherein:
the time-interleaved ADC is a single-level time-interleaved ADC;
the at least one ADC unit comprises only one ADC unit;
the digital gain controller samples a first digital output of the one ADC unit to create a first average;
the digital gain controller samples a second digital output of the one ADC unit to create a second average; and
the actual output is a difference between the first average and the second average.
12. The time-interleaved ADC of claim 1 , wherein:
the time-interleaved ADC is a dual-level time-interleaved ADC;
the at least one ADC unit comprises a plurality of ADC units;
the digital gain controller creates a first average from first digital outputs of a first subset of the plurality of ADC units corresponding to even ones of the plurality of ADC units;
the digital gain controller creates a second average from second digital outputs of a second subset of the plurality of ADC units corresponding to odd ones of the plurality of ADC units; and
the actual output is a difference between the first average and the second average.
13. The time-interleaved ADC of claim 1 , wherein:
the reference voltage is a differential reference voltage comprising a first reference voltage and a second reference voltage;
the digital gain controller increments both the first reference voltage and the second reference voltage when the comparison yields a first result;
the digital gain controller decrements both the first reference voltage and the second reference voltage when the comparison yields a second result;
the digital gain controller increments only one of the first reference voltage and the second reference voltage when the comparison yields a third result;
the digital gain controller decrements only one of the first reference voltage and the second reference voltage when the comparison yields a fourth result; and
the digital gain controller does not adjust either one of the first reference voltage and the second reference voltage when the comparison yields a fifth result.
14. A calibration circuit for a time-interleaved analog-to-digital converter (ADC), comprising:
a digital gain controller configured to compare an actual output of an ADC unit of the time-interleaved ADC to an expected output of the ADC unit; and
a digital-to-analog converter (DAC) structured to adjust a differential reference voltage for the ADC unit based on: (i) an initial differential reference voltage received from an interleaver circuit of the time-interleaved ADC, and (ii) at least one control signal generated by the digital gain controller based on the comparison.
15. A mixed-signal gain optimization loop in a time-interleaved analog-to-digital converter (ADC) apparatus, comprising:
a time-interleaved ADC having a sample rate of 1/T Samples/second and comprising a plurality of M ADC blocks each of which further comprises N ADC unit cells having a sample rate of 1/(M*N*T) Samples/second;
a circuit element configured to provide a reference voltage to be used as a full-scale reference for the N ADC unit cells in each of the M ADC blocks, wherein the reference voltage is a differential analog reference voltage defined by a difference between two absolute voltages taken with respect to a first power supply;
a reference voltage element configured to digitally adjust one or both of the absolute voltages; and
a digital calculation element configured to adjust a digital control of the reference voltage element, wherein:
the digital calculation element is operational during application of a predefined analog input signal to an input of the time-interleaved ADC;
the predefined analog input signal has two unique and predetermined levels differing from one another by a predefined nominal amount; and
the digital calculation element separately calculates:
a first average of digital outputs of even ones of the plurality of N ADC unit cells;
a second average of digital outputs of the odd ones of the plurality of N ADC unit cells;
a first difference between the first and second averages; and
a second difference between: the first difference and the predefined nominal amount.
16. A method of gain calibration of a time-interleaved analog-to-digital converter (ADC) apparatus, comprising:
providing a reference voltage to at least one ADC unit of the time-interleaved ADC, wherein the reference voltage is initially greater than a nominal full scale reference voltage range of the at least one ADC unit;
supplying a predefined analog input signal to the at least one ADC unit;
sampling an actual output of the at least one ADC unit generated based on the reference voltage and the predefined analog input signal;
comparing the actual output to an expected output associated with the predefined analog input signal; and
adjusting the reference voltage based on the comparing.
17. The method of claim 16 , further comprising iteratively repeating the sampling, the comparing, and the adjusting until a difference between the actual output and the expected output is within a predefined range.
18. The method of claim 16 , further comprising performing the steps of claim 17 when the time-interleaved ADC is off-line.
19. The method of claim 16 , wherein:
the actual output comprises a difference between first and second running averages of output of the at least one ADC unit that correspond to first and second levels of the predefined analog input signal; and
the comparing is insensitive to offset associated with the at least one ADC unit.
20. The method of claim 19 , wherein:
the time-interleaved ADC is a single-level time-interleaved ADC; and
the first and second running averages are based on consecutive digital outputs from the at least one ADC unit.
21. The method of claim 19 , wherein:
the time-interleaved ADC is a dual-level time-interleaved ADC;
the at least one ADC unit comprises a plurality of ADC sub-units; and
the first running average is based on digital outputs from a first subset of the plurality of ADC sub-units; and
the second running average is based on digital outputs from a second subset of the plurality of ADC sub-units.
22. The method of claim 16 , wherein:
the reference voltage is a differential reference voltage comprising first and second reference voltages; and
the adjusting comprises:
adjusting only one of the first and second reference voltages when the comparison yields a first predefined result; and
adjusting both the first and second reference voltages when the comparison yields a second predefined result.
23. The method of claim 16 , wherein the predefined analog input signal comprises a square wave with alternating high and low levels and an amplitude that is less than a full scale of the at least one ADC unit.
24. The method of claim 16 , wherein the predefined analog input signal comprises a pseudo random binary signal (PRBS).
25. A method of gain calibration of a time-interleaved analog-to-digital converter (ADC) apparatus, comprising:
providing a reference voltage to at least one ADC unit of the time-interleaved ADC, wherein the reference voltage is initially greater than a nominal full scale reference voltage range of the at least one ADC unit;
supplying a predefined analog input signal to the at least one ADC unit;
determining a first average of first digital outputs of the at least one ADC unit, wherein the first digital outputs correspond to a first level of the predefined analog input signal;
determining a second average of second digital outputs of the at least one ADC unit, wherein the second digital outputs correspond to a second level of the predefined analog input signal;
determining a difference between the first and second averages;
comparing the difference to an expected value for the predefined analog input signal; and
adjusting the reference voltage based on the comparing.