Memory device interface methods, apparatus, and systems
Apparatus and systems for memory system are provided. In an example, a memory system can include a plurality of memory dice and an interface chip. The memory dice can include a first memory die including a memory array coupled to through wafer interconnects (TWIs) and a second memory die, wherein the first memory die is stacked over the second memory die. In an example, the interface chip can be coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice. In an example, the interface chip can be configured to perform DRAM sequencing.
1. A memory system comprising:
a plurality of memory dice including:
a first memory die including a memory array coupled to through wafer interconnects (TWIs);
a second memory die, wherein the first memory die is stacked over the second memory die; and
an interface chip coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice, wherein the interface chip is configured to perform DRAM sequencing.
2. The memory system of claim 1 , wherein the second memory die is disposed on the interface chip and the first memory die is disposed on the second memory die.
3. The memory system of claim 1 , wherein the TWIs pass through vias within the second memory die to connect with the interface chip.
4. The memory system of claim 1 , wherein the second memory die is coupled to the interface chip using connection pins.
5. The memory system of claim 1 , including a substrate, wherein the interface chip is disposed on the substrate.
6. A memory system comprising:
a plurality of memory dice including:
a first memory die including a memory array coupled to through wafer interconnects (TWIs);
a second memory die, wherein the first memory die is stacked over the second memory die; and
an interface chip coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice, wherein the interface chip includes a multiplexer/demultiplexer circuit.
7. A memory system comprising:
a plurality of memory dice including:
a first memory die including a memory array coupled to through wafer interconnects (TWIs);
a second memory die, wherein the first memory die is stacked over the second memory die; and
an interface chip coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice, wherein the interface chip includes a plurality of memory controllers.
8. A memory system comprising:
a plurality of memory dice including:
a first memory die including a memory array coupled to through wafer interconnects (TWIs);
a second memory die, wherein the first memory die is stacked over the second memory die; and
an interface chip coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice, wherein the interface chip is configured to operate a refresh scheme.
9. A memory system comprising:
a plurality of memory dice including:
a first memory die including a memory array coupled to through wafer interconnects (TWIs);
a second memory die, wherein the first memory die is stacked over the second memory die; and
an interface chip coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice, wherein the interface chip is configured to operate a bad cell recovery scheme on the memory array.
10. A memory system comprising:
a plurality of memory dice including:
a first memory die including a memory array coupled to through wafer interconnects (TWIs);
a second memory die, wherein the first memory die is stacked over the second memory die; and
an interface chip coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice, wherein the interface chip includes a pattern generator configured to generate test pattern signals.
11. A memory system comprising:
a plurality of memory dice including:
a first memory die including a memory array coupled to through wafer interconnects (TWIs);
a second memory die, wherein the first memory die is stacked over the second memory die; and
an interface chip coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice, wherein the interface chip is configured to act as an interconnection device.
12. A memory system comprising:
a plurality of memory dice including:
a first memory die including a memory array coupled to through wafer interconnects (TWIs);
a second memory die, wherein the first memory die is stacked over the second memory die; and
an interface chip coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice, wherein the interface chip is configured to act as an I/O driver.
13. A memory system comprising:
a plurality of memory dice including:
a first memory die including a memory array coupled to through wafer interconnects (TWIs);
a second memory die, wherein the first memory die is stacked over the second memory die; and
an interface chip coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice, wherein the interface chip includes I/O pads.
14. The memory system of claim 13 , wherein the plurality of memory dice do not include I/O pads.
15. A memory system comprising:
a plurality of memory dice including:
a first memory die including a memory array coupled to through wafer interconnects (TWIs);
a second memory die, wherein the first memory die is stacked over the second memory die; and
an interface chip coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice, wherein the interface chip includes delayed-locked loop (DLL) circuitry.
16. The memory system of claim 15 , wherein the plurality of memory dice do not include DLL circuitry.
17. A memory system comprising:
a plurality of memory dice including:
a first memory die including a memory array coupled to through wafer interconnects (TWIs);
a second memory die, wherein the first memory die is stacked over the second memory die; and
an interface chip coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice, wherein the interface chip includes FIFO circuitry.
18. The memory system of claim 17 , wherein the plurality of memory dice do not include FIFO circuitry.
19. A memory system comprising:
a plurality of memory dice including:
a first memory die including a memory array coupled to through wafer interconnects (TWIs);
a second memory die, wherein the first memory die is stacked over the second memory die; and
an interface chip coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice,
wherein the interface chip is coupled to different memory banks within the plurality of memory dice with independent interconnects, and
wherein the interconnects include the TWIs.
20. A memory system comprising:
a plurality of memory dice including:
a first memory die including a memory array coupled to through wafer interconnects (TWIs);
a second memory die, wherein the first memory die is stacked over the second memory die; and
an interface chip coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice, wherein the interface chip is configured to transmit and receive test pattern signals between the interface chip and the plurality of memory dice.
21. A memory system comprising:
a plurality of memory dice including:
a first memory die including a memory array coupled to through wafer interconnects (TWIs);
a second memory die, wherein the first memory die is stacked over the second memory die; and
an interface chip coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice, wherein the interface chip is configured to perform power management within the memory system.
22. A memory system comprising:
a plurality of memory dice including:
a first memory die including a memory array coupled to through wafer interconnects (TWIs);
a second memory die, wherein the first memory die is stacked over the second memory die; and
an interface chip coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice, wherein the interface chip is configured to perform error detection and/or correction.
23. A memory system comprising:
a plurality of memory dice including:
a first memory die including a memory array coupled to through wafer interconnects (TWIs);
a second memory die, wherein the first memory die is stacked over the second memory die; and
an interface chip coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice, wherein the interface chip includes a Built in Self-Test (BIST) module.
24. The memory system of claim 23 , wherein the BIST module is coupled to a maintenance bus that is coupled between the interface chip and the plurality of memory dice.
25. The memory system of claim 24 , wherein the BIST module is configured to send command signals and data to the plurality of memory dice through the maintenance bus.