Dry etch polysilicon removal for replacement gates
Semiconductor devices are formed with a gate last, high-K/metal gate process with complete removal of the polysilicon dummy gate and with a gap having a low aspect ratio for the metal fill. Embodiments include forming a dummy gate electrode on a substrate, the dummy gate electrode having a nitride cap, forming spacers adjacent opposite sides of the dummy gate electrode forming a gate trench therebetween, dry etching the nitride cap, tapering the gate trench top corners; performing a selective dry etch on a portion of the dummy gate electrode, and wet etching the remainder of the dummy gate electrode.
1. A method comprising:
forming a dummy gate electrode on a substrate, the dummy gate electrode having a nitride cap;
forming spacers adjacent opposite sides of the dummy gate electrode, forming a gate trench therebetween;
dry etching the nitride cap;
tapering the gate trench top corners, subsequent to dry etching the nitride cap;
performing a selective dry etch on a portion of the dummy gate electrode, subsequent to tapering the gate trench top corners, the portion comprising a majority of the dummy gate electrode; and
wet etching the remainder of the dummy gate electrode, to prevent damage to layers underlying the dummy gate electrode.
2. The method according to claim 1 , wherein the dummy gate electrode comprises polysilicon.
3. The method according to claim 2 , comprising tapering the gate trench top corners by performing a non-selective dry etch on the polysilicon.
4. The method according to claim 3 , comprising sputtering argon at an angle of 30° to 60° for the non-selective dry etch.
5. The method according to claim 2 , wherein the selective dry etch is selective to oxide and nitride.
6. The method according to claim 2 , wherein the portion comprises 60% to 90% of the dummy gate electrode.
7. The method according to claim 2 , comprising wet etching with tetramethylammonium hydroxide (TMAH), ammonia, or ammonium hydroxide.
8. The method according to claim 2 , further comprising filling the gate trench with metal, subsequent to wet etching the remainder of the dummy gate electrode, to form a metal gate electrode.
9. The method according to claim 2 , comprising forming a high-K dielectric layer on the substrate prior to forming the dummy gate electrode.
10. The method according to claim 9 , further comprising forming a metal layer on the high-K dielectric layer prior to forming the dummy gate electrode.
11. A method comprising:
forming a dummy gate electrode on a substrate, the dummy gate electrode having a nitride cap;
forming spacers adjacent opposite sides of the dummy gate electrode, forming a gate trench therebetween;
dry etching the nitride cap;
performing a selective dry etch on a portion of the dummy gate electrode and concurrently tapering the gate trench top corners, subsequent to dry etching the nitride cap, the portion comprising a majority of the dummy gate electrode; and
wet etching the remainder of the dummy gate electrode, to prevent damage to layers underlying the dummy gate electrode.
12. The method according to claim 11 , wherein the dummy gate electrode comprises polysilicon.
13. The method according to claim 12 , comprising tapering the gate trench top corners by sputtering argon at an angle of 30° to 60° .
14. The method according to claim 12 , wherein the selective dry etch is selective to oxide and nitride.
15. The method according to claim 12 , wherein the portion comprises 60% to 90% of the dummy gate electrode.
16. The method according to claim 12 , comprising wet etching with tetramethylammonium hydroxide (TMAH), ammonia, or ammonium hydroxide.
17. The method according to claim 16 , further comprising filling the gate trench with metal, subsequent to wet etching the remainder of the dummy gate electrode, to form a metal gate electrode.
18. The method according to claim 12 , comprising forming a high-K dielectric layer on the substrate prior to forming the dummy gate electrode.
19. The method according to claim 18 , further comprising forming a metal layer on the high-K dielectric layer prior to forming the dummy gate electrode.
20. A method comprising:
forming high-K dielectric layers on a substrate;
forming a polysilicon gate electrode on each high-K dielectric layer;
forming a nitride cap on each polysilicon gate electrode;
forming spacers adjacent opposite sides of each polysilicon gate electrode, forming a gate trench therebetween;
filling space between adjacent polysilicon gate electrodes with an oxide interlayer dielectric;
dry etching the nitride caps with an etch chemistry that is selective to oxide;
sputtering argon at an angle of 30° to 60° to taper the gate trench top corners;
dry etching a portion of each dummy gate electrode with an etch chemistry that is selective to oxide and nitride;
wet etching the remainder of each dummy gate electrode, forming respective cavities; and
filling each cavity with a metal gate electrode.