Adaptive bias for low power low dropout voltage regulators

1. A low dropout (LDO) voltage regulator comprising:

a voltage regulation loop for providing a gate drive signal to an output device, the gate drive signal proportional to an output current, the voltage regulation loop including a current bias input for receiving an adaptive bias current; and

a current bias control circuit for providing the adaptive bias current at a first value that is proportional to a width-to-length ratio of transistors of a transconductance amplifier and a current applied to a first input of the transconductance amplifier, the current bias control circuit increases the adaptive bias current from a threshold to a current limit value, the output current varies substantially linearly over a range of output current values between the threshold and the current limit value.

2. The LDO voltage regulator of claim 1 , wherein the current bias control circuit comprises:

a current mirror including a first current flow path coupled to the current bias input, and a second current flow path; and

the transconductance amplifier including the first input for receiving a first voltage related to the current, a second input for receiving a second voltage, and an output coupled to the second current flow path for providing a bias control signal.

3. The LDO voltage regulator of claim 2 , wherein the transconductance amplifier comprises:

a first transistor including a drain coupled to a power supply terminal, a gate, and a source; and

a second transistor including a drain coupled to the second current flow path of the current mirror, a gate, and a source coupled to the source of the first transistor.

4. The LDO voltage regulator of claim 3 , further comprising:

a third transistor including a drain coupled to the sources of the first and second transistors, a gate for receiving a bias voltage, and a source coupled to the power supply terminal; and

wherein a second current flowing through the third transistor forms the current limit value.

5. The LDO voltage regulator of claim 1 , further comprising:

a first transistor including a source coupled to a power supply terminal, a gate coupled to the output of the transconductance amplifier, and a drain;

a second transistor including a source coupled to the drain of the first transistor, a gate, and a drain coupled to the current bias control circuit; and

a third transistor including a drain coupled to the drain of the first transistor, a gate for receiving a bias voltage, and a source coupled to a second power supply terminal; and

wherein a current flowing through the third transistor sets the threshold.

6. The LDO voltage regulator of claim 5 , further comprising:

a current mirror including a first current flow path coupled to the current bias input, and a second current flow path;

wherein the first input of the transconductance amplifier receives a first voltage and the transconductance amplifier also includes a second input for receiving a second voltage, and an output coupled to the second current flow path for providing a bias control signal;

a first bias circuit configured to provide the first voltage to the first input, the first voltage being substantially constant;

a second bias circuit configured to provide the second voltage to the second input; and

a current injection circuit coupled to the second input and configured to provide a supplemental bias voltage to the second input, the supplemental bias voltage related to the output current.

7. The LDO voltage regulator of claim 1 , wherein the voltage regulation loop comprises an amplifier including a first input for receiving a first reference voltage, a second input for receiving a feedback voltage, a control input for receiving the adaptive bias current, and an output for providing the gate drive signal.

8. The LDO voltage regulator of claim 1 , wherein the current bias control circuit comprises a current mirror comprising:

a first transistor including a source coupled to a power supply terminal, a gate, and a drain coupled to the current bias input for providing the bias current; and

a second transistor including a source coupled to the power supply terminal, a gate coupled to the gate of the first transistor, and a drain coupled to the gate of the first and second transistors,

wherein the first input of the transconductance amplifier receives a reference voltage, and the transconductance amplifier also includes a second input that varies as a function of the output current, and an output coupled to the drain of the second transistor.

9. A low dropout (LDO) voltage regulator comprising:

an amplifier including a first input for receiving a reference voltage, a second input for receiving a feedback signal, a bias current input and an output for providing a gate drive signal;

a current mirror including a first current path and a second current path, the first current path coupled to the bias current input of the amplifier; and

a transconductance amplifier including a first input for receiving a second reference voltage, a second input for receiving a voltage related to an output current, and an output coupled to the second current path of the current mirror for providing the output current as a function of a difference between the second reference voltage and the voltage related to the output current, the transconductance amplifier configured to control a current bias provided to the amplifier.

10. The LDO voltage regulator of claim 9 , wherein the transconductance amplifier comprises:

a first transistor including a drain coupled to a power supply terminal, a source, and a gate forming the first input for receiving the second reference voltage; and

a second transistor having a drain forming the output, a source coupled to the source of the first transistor, and a gate forming the second input for receiving the voltage related to the output current; and

a third transistor including a drain coupled to the sources of the first and second transistors, a gate for receiving a first bias voltage, and a source coupled to ground.

11. The LDO voltage regulator of claim 10 , wherein a current flowing through the third transistor defines a bias current limit.

12. The LDO voltage regulator of claim 9 , further comprising:

a first bias circuit coupled to the first input of the transconductance amplifier for providing the second reference voltage;

a second bias circuit coupled to the second input of the transconductance amplifier, the second bias circuit matched to the first bias circuit to provide a third reference voltage to the second input that is equal to the second reference voltage; and

a third bias circuit configured to provide a current proportional to the output current to the second input of the transconductance amplifier, the third bias circuit to provide a third voltage that combines with the third reference voltage to provide the voltage related to the output current.

13. The LDO voltage regulator of claim 12 , wherein the first bias circuit comprises:

a first transistor including a source coupled to a power supply terminal, a gate for receiving a second bias voltage, and a drain coupled to the first input of the transconductance amplifier;

a first resistor including a first terminal coupled to the drain of the first transistor, and a second terminal, a second voltage across the resistor forming the second reference voltage; and

a second transistor including a drain and a gate coupled to the second terminal of the first resistor, and a source coupled to ground.

14. The LDO voltage regulator of claim 13 , wherein the second bias circuit comprises:

a third transistor including a source coupled to the power supply terminal, a gate for receiving the second bias voltage, and a drain coupled to the second input of the transconductance amplifier;

a second resistor including a first terminal coupled to the drain of the third transistor, and a second terminal, a third voltage across the resistor forming the third reference voltage; and

a fourth transistor including a drain and a gate coupled to the second terminal of the second resistor, and a source coupled to ground.

15. The LDO voltage regulator of claim 14 , wherein the third bias circuit comprises:

a fifth transistor configured to match the output current to produce a proportional current, the fifth transistor including a source coupled to the power supply terminal, a gate coupled to the output of the amplifier, and a drain;

a sixth transistor including a source coupled to the drain of the fifth transistor, a gate, and a drain coupled to the second input of the transconductance amplifier; and

a seventh transistor including a drain coupled to the drain of the fifth transistor, a gate for receiving a first bias voltage, and a source coupled to ground; and

an eighth transistor including a drain coupled to the power supply terminal, a gate coupled to an output terminal, and a source coupled to the gate of the sixth transistor and to ground through a current source.

16. A low dropout (LDO) voltage regulator comprising:

an amplifier including a first input for receiving a reference voltage, a second input for receiving a feedback voltage, a current bias input, and an output for providing a gate drive signal;

a power transistor including a first current electrode for receiving a supply voltage; a control electrode coupled to the output of the amplifier, and a second current electrode coupled to an output terminal for providing an output current; and

an adaptive current bias circuit coupled to the current bias input and configured to provide an adaptive bias current having a first current level to the current bias input when the output current is less than a threshold, and, when the output current exceeds the threshold, increasing the adaptive bias current from the first current level along a substantially linear slope until a current limit is reached.

17. The LDO voltage regulator of claim 16 , further comprising a voltage divider circuit including:

a first resistor including a first terminal coupled to output terminal, and a second terminal coupled to the second input of the amplifier to provide the feedback voltage; and

a second resistor including a first terminal coupled to the second terminal of the first resistor, and a second terminal coupled to ground.

18. The LDO voltage regulator of claim 16 , wherein the adaptive current bias circuit provides a non-zero current when the output current is zero.

19. The LDO voltage regulator of claim 16 , wherein the adaptive current bias circuit comprises:

a current mirror including a first current flow path coupled to the current bias input, and a second current flow path, the current mirror to provide the adaptive bias current on the first current flow path that is proportional to a second current on the second current flow path; and

a transconductance amplifier including a first input for receiving a second reference voltage, a second input for receiving a second voltage that is proportional to the output current, and an output coupled to the second current flow path, the transconductance amplifier configured to provide the adaptive bias current as a function of a voltage between the second reference voltage and the second voltage.

20. The LDO voltage regulator of claim 19 , wherein the transconductance amplifier comprises:

a first transistor including a drain coupled to a power supply terminal, a gate for receiving the second reference voltage, and a source;

a second transistor including a drain coupled to the second current flow path, a gate for receiving the second voltage, and a source coupled to the source of the first transistor; and

a third transistor including a drain coupled to the sources of the first and second transistors, a gate for receiving a bias voltage, and a source coupled to ground; and

wherein current flowing through the third transistor sets the current limit.